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Travelled to:
1 × France
2 × Germany
Collaborated with:
F.Azaïs M.Renovell Y.Bertrand H.Ayari M.Comte V.Kerzerho E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart G.Moritz O.Billoint Y.Maneglia P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:
implement (2) histogram (1) silicon (1) predict (1) augment (1) voltag (1) redund (1) linear (1) design (1) deplet (1)

Person: Serge Bernard

DBLP DBLP: Bernard:Serge

Contributed to:

DATE 20142014
DATE 20132013
DATE 20012001

Wrote 3 papers:

DATE-2014-AyariABCKR #predict
New implementions of predictive alternate analog/RF test with augmented model redundancy (HA, FA, SB, MC, VK, MR), pp. 1–4.
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
DATE-2001-AzaisBBR #implementation #linear
Implementation of a linear histogram BIST for ADCs (FA, SB, YB, MR), pp. 590–595.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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