26 papers:
DATE-2011-LiMY #independence- Redressing timing issues for speed-independent circuits in deep submicron age (YL, TSTM, AY), pp. 1376–1381.
- DATE-2008-Schat #clustering #fault #process
- Fault Clustering in deep-submicron CMOS Processes (JS), pp. 511–514.
- DATE-2008-ZengC #analysis #polynomial #random
- Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis (JKZ, CPC), pp. 1091–1094.
- DATE-2006-NiclassSC #array
- A single photon avalanche diode array fabricated in deep-submicron CMOS technology (CN, MS, EC), pp. 81–86.
- DATE-2005-LiS #performance #simulation
- An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.
- DATE-2005-WangMDCM #analysis #embedded #energy #process #variability
- Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules (HW, MM, WD, FC, KM), pp. 914–919.
DAC-2004-EkpanyapongMWLL #architecture #design- Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.
- DATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis
- Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
- DATE-v2-2004-RosselloS
- A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
HPCA-2002-YangPFV #design #energy- Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (SHY, MDP, BF, TNV), pp. 151–161.
- DATE-2001-Bazargan-SabetI #modelling #tool support #verification
- Modeling crosstalk noise for deep submicron verification tools (PBS, FI), pp. 530–534.
- HPCA-2001-YangPFRV #approach #architecture
- An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.
- DAC-2000-LevyBBDGOOSZ #analysis #design #named
- ClariNet: a noise analysis tool for deep submicron design (RL, DB, GB, AD, AG, CO, BO, SS, VZ), pp. 233–238.
- DAC-1999-CongP #design #estimation
- Interconnect Estimation and Dlanning for Deep Submicron Designs (JC, DZP), pp. 507–510.
- DAC-1999-JiangC #analysis #performance #power management
- Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (YMJ, KTC), pp. 760–765.
- DAC-1999-YimK #design
- Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
- DATE-1999-NicolaidisZ #online #scalability #testing
- Scaling Deeper to Submicron: On-Line Testing to the Rescue (MN, YZ), p. 432–?.
- DATE-1999-ToulouseBLN #3d #modelling #performance
- Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts (AT, DB, CL, PN), pp. 576–580.
- DATE-1999-YeCFCNC #design #verification
- Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
- DATE-1998-Rodriguez-MontanesF #estimation
- Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs (RRM, JF), pp. 490–494.
- DAC-1997-ChenL #analysis #design #power management
- Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design (HHC, DDL), pp. 638–643.
- DAC-1997-ForzanFG #megamodelling #performance #standard
- Accurate and Efficient Macromodel of Submicron Digital Standard Cells (CF, BF, CG), pp. 633–637.
- DAC-1997-Man #education #question
- Education for the Deep Submicron Age: Business as Usual? (HDM), pp. 307–312.
- EDTC-1997-KunduG #analysis
- Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.
- DAC-1996-SatoKEM #design #optimisation
- Post-Layout Optimization for Deep Submicron Design (KS, MK, HE, NM), pp. 740–745.
- DAC-1989-MeijsG #finite #performance
- An Efficient Finite Element Method for Submicron IC Capacitance Extraction (NPvdM, AJvG), pp. 678–681.
