Travelled to:1 × Germany
2 × USA
Collaborated with:D.Sylvester D.Blaauw T.N.Mudge T.M.Austin M.Anders S.Hsu A.Agarwal R.Krishnamurthy S.Borkar
Talks about:design (3) challeng (2) threshold (1) opportun (1) perform (1) nanomet (1) correct (1) voltag (1) futur (1) error (1)
Person: Himanshu Kaul
DBLP: Kaul:Himanshu
Contributed to:
2012
20052001Wrote 3 papers:
- DAC-2012-KaulAHAKB #challenge #design
- Near-threshold voltage (NTV) design: opportunities and challenges (HK, MA, SH, AA, RK, SB), pp. 1153–1158.
- DATE-2005-KaulSBMA #design #fault
- DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.
- DAC-2001-SylvesterK #challenge #design #performance
- Future Performance Challenges in Nanometer Design (DS, HK), pp. 3–8.