30 papers:
DATE-2013-GielenM #modelling #probability #simulation- Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.
- DATE-2011-GielenMW #analysis #reliability
- Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation (GGEG, EM, PHNDW), pp. 1474–1479.
- DATE-2009-LadharMB #fault #performance
- Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data (AL, MM, LB), pp. 988–993.
- DATE-2009-SathanurPBMM #clustering #design #variability
- Physically clustered forward body biasing for variability compensation in nanometer CMOS design (AVS, AP, LB, GDM, EM), pp. 154–159.
- DATE-2009-SreedharK #analysis #on the
- On linewidth-based yield analysis for nanometer lithography (AS, SK), pp. 381–386.
- DATE-2008-GielenWMLMKGRN #challenge #reliability
- Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies (GGEG, PHNDW, EM, JL, JMM, BK, GG, RR, MN), pp. 1322–1327.
DAC-2007-AgarwalN #process- Characterizing Process Variation in Nanometer CMOS (KA, SRN), pp. 396–399.
- DAC-2007-HansonSSB #scalability
- Nanometer Device Scaling in Subthreshold Circuits (SH, MS, DS, DB), pp. 700–705.
- DATE-2007-RosselloBBS #statistics #testing
- Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs (JLR, CdB, SAB, JS), pp. 1271–1276.
- DATE-2007-ZhuZCXZ #grid #probability #process
- A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology (HZ, XZ, WC, JX, DZ), pp. 1514–1519.
- DAC-2006-NassifPRSBR #analysis #question
- Variation-aware analysis: savior of the nanometer era? (SRN, VP, NR, DS, CB, RR), pp. 411–412.
- DAC-2006-SingerMBHK #question #what
- The IC nanometer race — what will it take to win? (GS, PM, DB, FCH, HKK), pp. 77–78.
- DAC-2006-VattikondaWC #design #modelling #robust
- Modeling and minimization of PMOS NBTI effect for robust nanometer design (RV, WW, YC), pp. 1047–1052.
- DATE-2006-ChenMBR #case study #design #power management
- Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design (QC, SM, AB, KR), pp. 983–988.
- DATE-2005-BaiKKSM #multi #trade-off
- Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (RB, NSK, TK, DS, TNM), pp. 650–651.
- DATE-2005-DhillonDC #analysis #optimisation
- Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits (YSD, AUD, AC), pp. 288–293.
- DATE-2005-Hughes #challenge
- Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges (GH), p. 3.
HPCA-2005-SundaresanM #energy #modelling- Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses (KS, NRM), pp. 51–60.
- DAC-2004-BorkarKD #challenge #design #reliability
- Design and reliability challenges in nanometer technologies (SB, TK, VD), p. 75.
- DAC-2004-ChoiPR #algorithm #novel #process
- Novel sizing algorithm for yield improvement under process variation in nanometer technology (SHC, BCP, KR), pp. 454–459.
- DATE-v2-2004-RajskiT #design #question #requirements #what
- Nanometer Design: What are the Requirements for Manufacturing Test? (JR, KT), pp. 930–937.
- DAC-2003-BittlestoneHSA #architecture #library
- Architecting ASIC libraries and flows in nanometer era (CB, AMH, VS, NVA), pp. 776–781.
- DAC-2003-KahngBCDGSS #design
- Nanometer design: place your bets (ABK, SB, JMC, AD, PG, LS, JPS), pp. 546–547.
- DAC-2003-MagarshackP
- System-on-chip beyond the nanometer wall (PM, PGP), pp. 419–424.
- DAC-2002-BrodersenHKKLK #design #question #what
- Nanometer design: what hurts next...? (RWB, AMH, JK, DK, MAL, MK), p. 242.
- DAC-2001-Maly #design
- IC Design in High-Cost Nanometer-Technologies Era (WM), pp. 9–14.
- DAC-2001-SylvesterK #challenge #design #performance
- Future Performance Challenges in Nanometer Design (DS, HK), pp. 3–8.
- DAC-2001-TaylorDZ #energy #modelling
- Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (CNT, SD, YZ), pp. 754–757.
ICPR-v3-2000-DoelVHVYGK #analysis #metric- Nanometer-Scale Height Measurements in Micromachined Picoliter Vials Based on Interference Fringe Analysis (LRVdD, LJvV, KTH, MJV, ITY, FG, JGK), pp. 3057–3062.
- DATE-1999-Williams #testing
- Testing in Nanometer Technologies (TWW), p. 5–?.
