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Travelled to:
12 × USA
3 × France
4 × Germany
Collaborated with:
D.Blaauw K.Agarwal A.Srivastava A.B.Kahng P.Gupta T.N.Mudge V.Veetil J.Yang R.R.Rao M.Seok H.Kaul S.Shah R.Gandikota L.Capodieci S.Hanson H.Deogun D.Lee D.Fick R.G.Dreslinski K.Chopra Y.Kim V.Joshi Y.Kim C.Zhuo A.DeOrio V.Bertacco M.R.Guthaus R.B.Brown S.R.Nassif A.K.Sultania S.S.Sapatnekar S.Satpathy Y.Wang H.Yu P.Kong Y.Chang E.Karl P.Sharma A.Devgan B.Zhai K.Flautner W.Kwong Y.Lee D.Yoon D.Jeon C.Chakrabarti S.Rochel B.Cline M.R.Becer R.Bai N.S.Kim T.Kgil T.M.Austin R.Das V.Sukharev A.Torres J.Hu G.K.Chen V.Pitchumani N.Rodriguez C.Bittlestone R.Radojcic S.W.Director F.Liu S.B.K.Vrudhula N.R.Pinckney K.Sewell C.Chen Z.Zhang H.Naeimi S.Sandhu M.Woh D.Kershaw M.Wieckowski V.Chandra S.Idgunji C.Pietrzyk R.C.Aitken R.Puri L.Stok J.M.Cohn D.S.Kung D.Z.Pan S.H.Kulkarni J.M.Rabaey K.Bernstein J.Frenkil M.Horowitz W.Nebel T.Sakurai A.Yang A.E.Caldwell Y.Cao F.Koushanfar H.Lu I.L.Markov M.Oliver D.Stroobandt
Talks about:
power (12) analysi (11) leakag (11) base (11) circuit (7) effici (7) design (7) variat (6) consid (6) time (6)

Person: Dennis Sylvester

DBLP DBLP: Sylvester:Dennis

Contributed to:

DATE 20142014
DAC 20122012
DAC 20112011
DATE 20112011
DAC 20102010
DATE 20102010
DAC 20092009
DATE 20092009
DAC 20082008
DAC 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DATE v1 20042004
DAC 20032003
DAC 20012001
DAC 20002000

Wrote 49 papers:

DATE-2014-WangYSK #encryption #energy #in memory #performance
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire (YW, HY, DS, PK), pp. 1–4.
DAC-2012-LeeKYBS #design #guidelines #power management
Circuit and system design guidelines for ultra-low power sensor nodes (YL, YK, DY, DB, DS), pp. 1037–1042.
DAC-2012-PinckneySDFMSB #performance
Assessing the performance limits of parallelized near-threshold computing (NRP, KS, RGD, DF, TNM, DS, DB), pp. 1147–1152.
DAC-2012-SatpathyDDMSB #multi #quality #self
High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service (SS, RD, RGD, TNM, DS, DB), pp. 406–411.
DAC-2011-SeokJCBS #design #energy #performance #pipes and filters
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design (MS, DJ, CC, DB, DS), pp. 990–995.
A confidence-driven model for error-resilient computing (CHC, YK, ZZ, DB, DS, HN, SS), pp. 1608–1613.
DATE-2011-WohSDKSBM #power management
Low power interconnects for SIMD computers (MW, SS, RGD, DK, DS, DB, TNM), pp. 600–605.
DAC-2010-JoshiSTASB #modelling
Closed-form modeling of layout-dependent mechanical stress (VJ, VS, AT, KA, DS, DB), pp. 673–678.
DAC-2010-VeetilCSB #monte carlo #performance #resource management
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization (VV, YHC, DS, DB), pp. 793–798.
DATE-2010-WieckowskiSBCIPA #analysis #black box
A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.
DATE-2010-ZhuoSB #process #reliability
Process variation and temperature-aware reliability management (CZ, DS, DB), pp. 580–585.
DAC-2009-FickDHBBS #named #network #reliability
Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.
DAC-2009-VeetilSBSR #analysis #dependence #performance
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence (VV, DS, DB, SS, SR), pp. 154–159.
DATE-2009-FickDCBSB #algorithm #fault tolerance
A highly resilient routing algorithm for fault-tolerant NoCs (DF, AD, GKC, VB, DS, DB), pp. 21–26.
DAC-2008-GandikotaBS #analysis #modelling #statistics
Modeling crosstalk in statistical static timing analysis (RG, DB, DS), pp. 974–979.
DAC-2008-JoshiCSBA #power management #reduction #using
Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
DAC-2008-VeetilSB #analysis #incremental #monte carlo #performance #statistics
Efficient Monte Carlo based incremental statistical timing analysis (VV, DS, DB), pp. 676–681.
DAC-2007-GandikotaCBSB #analysis #set
Top-k Aggressors Sets in Delay Noise Analysis (RG, KC, DB, DS, MRB), pp. 174–179.
Line-End Shortening is Not Always a Failure (PG, ABK, YK, SS, DS), pp. 270–271.
DAC-2007-HansonSSB #scalability
Nanometer Device Scaling in Subthreshold Circuits (SH, MS, DS, DB), pp. 700–705.
DAC-2007-SeokHSB #analysis #design #optimisation
Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design (MS, SH, DS, DB), pp. 694–699.
DAC-2006-GuthausSB #programming #using
Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.
DAC-2006-KarlBSM #modelling #reliability
Reliability modeling and management in dynamic microprocessor-based systems (EK, DB, DS, TNM), pp. 1057–1060.
DAC-2006-NassifPRSBR #analysis #question
Variation-aware analysis: savior of the nanometer era? (SRN, VP, NR, DS, CB, RR), pp. 411–412.
DATE-2006-RaoCBS #algorithm #fault #performance
An efficient static algorithm for computing the soft error rates of combinational circuits (RRR, KC, DB, DS), pp. 164–169.
DAC-2005-GuptaKKS #analysis
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions (PG, ABK, YK, DS), pp. 365–368.
DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
DAC-2005-YangCS #analysis
Advanced timing analysis based on post-OPC extraction of critical dimensions (JY, LC, DS), pp. 359–364.
DATE-2005-BaiKKSM #multi #trade-off
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (RB, NSK, TK, DS, TNM), pp. 650–651.
DATE-2005-KaulSBMA #design #fault
DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.
DAC-2004-AgarwalSBLNV #analysis #metric
Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2004-CapodieciGKSY #design #towards
Toward a methodology for manufacturability-driven design rule exploration (LC, PG, ABK, DS, JY), pp. 311–316.
DAC-2004-DeogunRSB #encoding #reduction
Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.
DAC-2004-GuptaKSS #effectiveness #runtime
Selective gate-length biasing for cost-effective runtime leakage control (PG, ABK, PS, DS), pp. 327–330.
DAC-2004-RaoDBS #estimation #parametricity #variability
Parametric yield estimation considering leakage variability (RRR, AD, DB, DS), pp. 442–447.
DAC-2004-SrivastavaSB #optimisation #power management #process #statistics #using
Statistical optimization of leakage power considering process variations using dual-Vth and sizing (AS, DS, DB), pp. 773–778.
DAC-2004-SrivastavaSB04a #power management #using
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
DAC-2004-SultaniaSS #trade-off
Tradeoffs between date oxide leakage and delay for dual Tox circuits (AKS, DS, SSS), pp. 761–766.
DAC-2004-ZhaiBSF #scalability
Theoretical and practical limits of dynamic voltage scaling (BZ, DB, DS, KF), pp. 868–873.
DATE-v1-2004-LeeDBS #power management
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization (DL, HD, DB, DS), pp. 494–499.
DATE-v1-2004-SrivastavaSB #concurrent #design #power management
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DAC-2003-AgarwalSB #effectiveness
An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
DAC-2003-AgarwalSB03a #metric
Simple metrics for slew rate of RC circuits based on two circuit moments (KA, DS, DB), pp. 950–953.
DAC-2003-GuptaKSY #off the shelf #tool support
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools (PG, ABK, DS, JY), pp. 16–21.
DAC-2003-LeeKBS #analysis
Analysis and minimization techniques for total leakage considering gate oxide leakage (DL, WK, DB, DS), pp. 175–180.
DAC-2003-PuriSCKPSSK #performance
Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.
Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
DAC-2001-SylvesterK #challenge #design #performance
Future Performance Challenges in Nanometer Design (DS, HK), pp. 3–8.
DAC-2000-CaldwellCKKLMOSS #named
GTX: the MARCO GSRC technology extrapolation system (AEC, YC, ABK, FK, HL, ILM, MO, DS, DS), pp. 693–698.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.