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Travelled to:
1 × France
1 × USA
2 × Germany
Collaborated with:
G.Jerke T.Meister G.Thomke J.Scheible T.Adler
Talks about:
analog (3) electromigr (2) current (2) circuit (2) driven (2) pin (2) decompact (1) arbitrari (1) algorithm (1) hierarch (1)

Person: Jens Lienig

DBLP DBLP: Lienig:Jens

Contributed to:

DATE 20082008
DAC 20042004
DATE 20022002
DATE 20012001

Wrote 4 papers:

DATE-2008-MeisterLT #algorithm #component #novel
Novel Pin Assignment Algorithms for Components with Very High Pin Counts (TM, JL, GT), pp. 837–842.
DAC-2004-JerkeLS #design #layout
Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs (GJ, JL, JS), pp. 181–184.
DATE-2002-JerkeL #analysis #verification
Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits (GJ, JL), pp. 464–469.
DATE-2001-LienigJA #approach #named
AnalogRouter: a new approach of current-driven routing for analog circuits (JL, GJ, TA), p. 819.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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