Stem pin$ (all stems)

53 papers:

CASE-2015-RoyelYLLH #identification #optimisation #parametricity #using

A hysteresis model and parameter identification for MR pin joints using immune particle swarm optimization (SR, YY, YL, JL, QPH), pp. 1319–1324.

DAC-2015-XuYGHP #named #self

PARR: pin access planning and regular routing for self-aligned double patterning (XX, BY, JRG, CLH, DZP), p. 6.

DATE-2015-KunduBK #design #fault #testing

Fault diagnosis in designs with extreme low pin test data compressors (SK, PB, RK), pp. 1285–1288.

CHI-2015-ZezschwitzLBH #named #performance #smarttech

SwiPIN: Fast and Secure PIN-Entry on Smartphones (EvZ, ADL, BB, HH), pp. 1403–1406.

ISMM-2015-OsterlundL #concurrent #protocol #using

Concurrent compaction using a field pinning protocol (EÖ, WL), pp. 56–69.

DATE-2014-DinhYH #design #logic

A logic integrated optimal pin-count design for digital microfluidic biochips (TAD, SY, TYH), pp. 1–6.

GPCE-2014-HillF #framework #object-oriented

Pin++: an object-oriented framework for writing pintools (JHH, DCF), pp. 133–141.

CGO-2014-ChabbiLM #tool support

Call Paths for Pin Tools (MC, XL, JMMC), p. 76.

DAC-2013-GrissomB #programmable

A field-programmable pin-constrained digital microfluidic biochip (DG, PB), p. 9.

CHI-2013-NicholsonCB #authentication #performance

Age-related performance issues for PIN and face-based authentication systems (JN, LMC, PB), pp. 323–332.

DAC-2012-LuoC #design

Design of pin-constrained general-purpose digital microfluidic biochips (YL, KC), pp. 18–25.

DAC-2012-QiuM #question #scalability

Can pin access limit the footprint scaling? (XQ, MMS), pp. 1100–1106.

DATE-2012-RichterC #manycore #reduction

Test pin count reduction for NoC-based Test delivery in multicore SOCs (MR, KC), pp. 787–792.

CGO-2012-LueckPP #debugging #interface #named

PinADX: an interface for customizable debugging with dynamic instrumentation (GL, HP, CP), pp. 114–123.

DAC-2011-HuangSH #power management

Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips (TWH, HYS, TYH), pp. 741–746.

DAC-2011-Nieberg

Gridless pin access in detailed routing (TN), pp. 170–175.

DATE-2011-TsaiLCKCK #bound #on the

On routing fixed escaped boundary pins for high speed boards (TYT, RJL, CYC, CYK, HMC, YK), pp. 461–466.

DAC-2010-LinC #design

Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips (CCYL, YWC), pp. 641–646.

CHI-2010-LucaHH #named

ColorPIN: securing PIN entry through indirect input (ADL, KH, HH), pp. 1103–1106.

CGO-2010-PatilPSLC #analysis #framework #named #parallel #source code

PinPlay: a framework for deterministic replay and reproducible analysis of parallel programs (HP, CP, MS, GL, JC), pp. 2–11.

DAC-2009-LinC #design

ILP-based pin-count aware design methodology for microfluidic biochips (CCYL, YWC), pp. 258–263.

DATE-2009-WuM #logic #order #performance

Joint logic restructuring and pin reordering against NBTI-induced performance degradation (KCW, DM), pp. 75–80.

ICDAR-2009-PalRRK #automation #multi #recognition #string

Indian Multi-Script Full Pin-code String Recognition for Postal Automation (UP, RKR, KR, FK), pp. 456–460.

DLT-2009-AlmeidaS #matrix

Matrix Mortality and the Cerný-Pin Conjecture (JA, BS), pp. 67–80.

HCI-VAD-2009-Peters #experience #performance

Influence of Real-World Ten-Pin Bowling Experience on Performance during First-Time Nintendo Wii Bowling Practice (KAP), pp. 396–405.

DAC-2008-XuC #multi

Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips (TX, KC), pp. 173–178.

DATE-2008-MeisterLT #algorithm #component #novel

Novel Pin Assignment Algorithms for Components with Very High Pin Counts (TM, JL, GT), pp. 837–842.

ASPLOS-2008-SrikantaiahKI #adaptation #multi #set

Adaptive set pinning: managing shared caches in chip multiprocessors (SS, MTK, MJI), pp. 135–144.

DAC-2007-Ozdal #clustering

Escape Routing For Dense Pin Clusters In Integrated Circuits (MMO), pp. 49–54.

DATE-2007-XuC #array

A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays (TX, KC), pp. 552–557.

ICEIS-DISI-2007-SantosB #clustering #named #optimisation

PIN: A partitioning and indexing optimization method for olap (RJS, JB), pp. 170–177.

CGO-2007-WallaceH #named #performance #realtime

SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance (SW, KMH), pp. 209–220.

DAC-2006-HwangSC #array #automation #design

Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications* (WLH, FS, KC), pp. 925–930.

OOPSLA-2006-Titzer #named

Virgil: objects on the head of a pin (BT), pp. 191–208.

PLDI-2005-LukCMPKLWRH #named #program analysis #tool support

Pin: building customized program analysis tools with dynamic instrumentation (CKL, RSC, RM, HP, AK, PGL, SW, VJR, KMH), pp. 190–200.

DAC-2004-ZhaoFZSP #power management

Optimal placement of power supply pads and pins (MZ, YF, VZ, SS, RP), pp. 165–170.

DATE-v2-2004-MinzPL #3d

Net and Pin Distribution for 3D Package Global Routing (JRM, MP, SKL), pp. 1410–1411.

DATE-v2-2004-TehranipourNC #flexibility #testing

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression (MHT, MN, KC), pp. 1284–1289.

DAC-2002-XiangWT #algorithm

An algorithm for integrated pin assignment and buffer planning (HX, DFW, XT), pp. 584–589.

DATE-2002-ChandraC #clustering #testing

Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression (AC, KC), pp. 598–603.

DAC-1999-CongHX #performance

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.

DAC-1992-HongHCK #algorithm #named #performance

FARM: An Efficient Feed-Through Pin Assignment Algorithm (XH, JH, CKC, ESK), pp. 530–535.

DAC-1992-HouC #algorithm #permutation

A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing (CYH, CYRC), pp. 594–599.

DAC-1992-HungP #constraints #design #multi #synthesis

High-Level Synthesis with Pin Constraints for Multiple-Chip Designs (YHH, ACP), pp. 231–234.

DAC-1988-YaoYL #approach #problem

A New Approach to the Pin Assignment Problem (XY, MY, CLL), pp. 566–572.

DAC-1980-KarpovskyS #component #detection #fault #standard

Detecting bridging and stuck-at faults at input and output pins of standard digital components (MGK, SYHS), pp. 494–505.

DAC-1978-Mory-Rauch

Pin assignment on a printed circuit board (LMR), pp. 70–73.

DAC-1976-Zobniw #multi #realtime #using

Multi-defect real time diagnosis using a single pin probe (LMZ), pp. 179–185.

DAC-1975-Zobniw #realtime #using

Real time diagnosis using single pin probe (LMZ), pp. 268–285.

DAC-1973-So #multi

Pin assignment of circuit cards and the routability of multilayer printed wiring backplanes (HCS), pp. 33–43.

DAC-1972-Koren #automation #design

Pin assignment in automated printed circuit board design (NLK), pp. 72–79.

DAC-1970-Sr #analysis #clustering #graph #logic #reduction

Partitioning of logic graphs: A theoretical analysis of pin reduction (RBHS), pp. 54–63.

DAC-1969-Radke #predict

A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios (CER), pp. 257–267.