BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
8 × USA
Collaborated with:
D.L.Dill E.M.Clarke K.L.McMillan A.Kölbl C.Pixley D.E.Long Y.Hong P.A.Beerel L.J.Hwang
Talks about:
verifi (4) model (4) check (4) symbol (3) use (3) microprocessor (2) properti (2) circuit (2) verif (2) superscalar (1)

Person: Jerry R. Burch

DBLP DBLP: Burch:Jerry_R=

Contributed to:

DAC 20072007
DAC 19971997
DAC 19961996
CAV 19941994
DAC 19911991
CAV 19901990
DAC 19901990
LICS 19901990

Wrote 9 papers:

DAC-2007-KoelblBP #equivalence #memory management #modelling
Memory Modeling in ESL-RTL Equivalence Checking (AK, JRB, CP), pp. 205–209.
DAC-1997-HongBBM #using
Safe BDD Minimization Using Don’t Cares (YH, PAB, JRB, KLM), pp. 208–213.
DAC-1996-Burch #verification
Techniques for Verifying Superscalar Microprocessors (JRB), pp. 552–557.
CAV-1994-BurchD #automation #pipes and filters #verification
Automatic verification of Pipelined Microprocessor Control (JRB, DLD), pp. 68–80.
DAC-1991-Burch #multi #using #verification
Using BDDs to Verify Multipliers (JRB), pp. 408–412.
DAC-1991-BurchCL #model checking #representation
Representing Circuits More Efficiently in Symbolic Model Checking (JRB, EMC, DEL), pp. 403–407.
CAV-1990-Burch #liveness #safety #verification
Verifying Liveness Properties by Verifying Safety Properties (JRB), pp. 224–232.
DAC-1990-BurchCMD #model checking #using #verification
Sequential Circuit Verification Using Symbolic Model Checking (JRB, EMC, KLM, DLD), pp. 46–51.
LICS-1990-BurchCMDH #model checking
Symbolic Model Checking: 10^20 States and Beyond (JRB, EMC, KLM, DLD, LJH), pp. 428–439.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.