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Travelled to:
1 × Portugal
4 × France
4 × Germany
7 × USA
Collaborated with:
J.Henkel L.Bauer S.Rehman M.U.K.Khan F.Kriebel S.Parameswaran S.Bampi B.Zatt H.Javaid S.Pagani D.Sun H.Khdr W.Ahmed H.Bokhari P.V.Aceituno F.Sampaio S.Garg D.Gnad J.Chen H.Amrouch L.V.Agostini B.Vogel B.Molkenthin T.Li J.A.Ambrose W.Ahmad R.Hafiz A.O.Tüfek S.Iqtedar O.Hasan D.Marculescu A.K.Singh A.Kumar M.Grellert S.Kreutz S.Kramer C.M.Diniz F.V.Dalcin H.Zhang T.Ebi D.Palomino A.A.Susin J.M.Borrmann F.L.Walter X.Zhang J.Peddersen M.R.K.K.Rao S.Junaidu T.Maghrabi M.Ahmed K.A.Faisal R.König T.Stripf J.Becker N.Dutt P.Gupta S.R.Nassif M.B.Tahoori N.Wehn S.Radhakrishnan R.G.Ragel
Talks about:
video (16) effici (12) adapt (12) system (10) code (10) chip (10) silicon (9) dark (9) processor (8) reliabl (8)

Person: Muhammad Shafique

DBLP DBLP: Shafique:Muhammad

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DATE 20092009
DAC 20082008
DATE 20082008
DAC 20072007
ITiCSE 20052005

Wrote 51 papers:

DAC-2015-BokhariJSHP #architecture #manycore #named
SuperNet: multimode interconnect architecture for manycore chips (HB, HJ, MS, JH, SP), p. 6.
DAC-2015-GnadSKRSH #named #variability
Hayat: harnessing dark silicon and variability for aging deceleration and balancing (DG, MS, FK, SR, DS, JH), p. 6.
DAC-2015-HenkelKPS #roadmap
New trends in dark silicon (JH, HK, SP, MS), p. 6.
DAC-2015-KhdrPSH #resource management
Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.
DAC-2015-ShafiqueAHH #configuration management #latency
A low latency generic accuracy configurable adder (MS, WA, RH, JH), p. 6.
DAC-2015-ShafiqueKTH #anti #energy #named #video
EnAAM: energy-efficient anti-aging for on-chip video memories (MS, MUKK, AOT, JH), p. 6.
DATE-2015-BokhariJSHP #adaptation
Malleable NoC: dark silicon inspired adaptable Network-on-Chip (HB, HJ, MS, JH, SP), pp. 1245–1248.
DATE-2015-DinizSDBH #architecture #hardware #performance #standard #video
A deblocking filter hardware architecture for the high efficiency video coding standard (CMD, MS, FVD, SB, JH), pp. 1509–1514.
DATE-2015-IqtedarHSH #analysis #distributed #probability
Formal probabilistic analysis of distributed dynamic thermal management (SI, OH, MS, JH), pp. 1221–1224.
DATE-2015-KhanSH #adaptation #manycore #power management
Power-efficient accelerator allocation in adaptive dark silicon many-core systems (MUKK, MS, JH), pp. 916–919.
DATE-2015-KriebelRSASH #analysis #combinator #configuration management #fault #named #performance
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits (FK, SR, DS, PVA, MS, JH), pp. 824–829.
DATE-2015-PaganiCSH #modelling #named #performance
MatEx: efficient transient and peak temperature computation for compact thermal models (SP, JJC, MS, JH), pp. 1515–1520.
DATE-2015-ShafiqueGGH #manycore #variability
Variability-aware dark silicon management in on-chip many-core systems (MS, DG, SG, JH), pp. 387–392.
DATE-2015-ZhangJSPHP #hardware #manycore #named #pipes and filters
E-pipeline: elastic hardware/software pipelines on a many-core fabric (XZ, HJ, MS, JP, JH, SP), pp. 363–368.
DAC-2014-BokhariJSHP #design #energy #multi #named
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon (HB, HJ, MS, JH, SP), p. 6.
DAC-2014-HenkelBZRS #architecture #dependence #multi
Multi-Layer Dependability: From Microarchitecture to Application Level (JH, LB, HZ, SR, MS), p. 6.
DAC-2014-KriebelRSSH #adaptation #fault #named
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era (FK, SR, DS, MS, JH), p. 6.
DAC-2014-RehmanKSSH #adaptation #code generation #dependence #named #process #reliability
dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects (SR, FK, DS, MS, JH), p. 6.
DAC-2014-ShafiqueGHM #challenge #reliability #variability
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives (MS, SG, JH, DM), p. 6.
DATE-2014-KhanSH #architecture #manycore #performance #power management #video
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing (MUKK, MS, JH), pp. 1–6.
DATE-2014-KhdrESAH #multi #named
mDTM: Multi-objective dynamic thermal management for on-chip systems (HK, TE, MS, HA, JH), pp. 1–6.
DATE-2014-PalominoSASH #named #performance #video
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding (DP, MS, HA, AAS, JH), pp. 1–4.
DATE-2014-RehmanKSH #compilation #reliability
Compiler-driven dynamic reliability management for on-chip systems under variabilities (SR, FK, MS, JH), pp. 1–4.
DATE-2014-SampaioSZBH #architecture #distributed #energy #memory management #named #performance #video
dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding (FS, MS, BZ, SB, JH), pp. 1–6.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap
Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-ShafiqueRAH #fault #optimisation #reliability
Exploiting program-level masking and error propagation for constrained reliability optimization (MS, SR, PVA, JH), p. 9.
DAC-2013-SinghSKH #manycore #overview #roadmap
Mapping on multi/many-core systems: survey of current and emerging trends (AKS, MS, AK, JH), p. 10.
DATE-2013-KhanBBSH #video
An H.264 Quad-FullHD low-latency intra video encoder (MUKK, JMB, LB, MS, JH), pp. 115–120.
DATE-2013-KhanSGH #collaboration #complexity #reduction
Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder (MUKK, MS, MG, JH), pp. 125–128.
DATE-2013-LiSRRRAHP #configuration management #named
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-RehmanSAKCH #hardware #reliability
Leveraging variable function resilience for selective software reliability on unreliable hardware (SR, MS, PVA, FK, JJC, JH), pp. 1759–1764.
DATE-2013-SampaioZSABH #energy #estimation #memory management #multi #video
Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding (FS, BZ, MS, LVA, SB, JH), pp. 665–670.
DATE-2013-ShafiqueVH #adaptation #hybrid #manycore #power management #self
Self-adaptive hybrid dynamic power management for many-core systems (MS, BV, JH), pp. 51–56.
DAC-2012-RehmanSH #compilation #scheduling
Instruction scheduling for reliability-aware compilation (SR, MS, JH), pp. 1292–1300.
DAC-2012-ShafiqueZWBH #adaptation #memory management #multi #power management #video
Adaptive power management of on-chip video memory for multiview video coding (MS, BZ, FLW, SB, JH), pp. 866–875.
DATE-2012-ShafiqueZRKH #adaptation #power management
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding (MS, BZ, SR, FK, JH), pp. 697–702.
DAC-2011-JavaidSPH #adaptation #case study #multi #pipes and filters #power management #video
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study (HJ, MS, SP, JH), pp. 1032–1037.
DAC-2011-ZattSSABH #adaptation #energy #estimation #multi #runtime #video
Run-time adaptive energy-aware motion and disparity estimation in multiview video coding (BZ, MS, FS, LVA, SB, JH), pp. 1026–1031.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-ShafiqueBAH #configuration management #manycore #resource management #runtime
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors (MS, LB, WA, JH), pp. 1261–1266.
DATE-2011-ZattSBH #architecture #estimation #hardware #parallel #pipes and filters #throughput #video
Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding (BZ, MS, SB, JH), pp. 1448–1453.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
DATE-2010-ShafiqueBH #adaptation #energy #estimation #named #predict #runtime #video
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder (MS, LB, JH), pp. 1725–1730.
DATE-2010-ShafiqueMH #adaptation #complexity #reduction #using #video
An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion (MS, BM, JH), pp. 1713–1718.
DATE-2009-BauerSH #architecture #configuration management #design
Cross-architectural design space exploration tool for reconfigurable processors (LB, MS, JH), pp. 958–963.
DATE-2009-ShafiqueBH #approach #design #hardware #parallel #performance #predict #video
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DAC-2008-BauerSH #embedded #runtime #set
Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DATE-2008-BauerSKH #embedded #runtime #set
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DAC-2007-BauerSKH #framework #named #platform #set
RISPP: Rotating Instruction Set Processing Platform (LB, MS, SK, JH), pp. 791–796.
ITiCSE-2005-RaoJMSAF #case study #design #education #implementation
Principles of curriculum design and revision: a case study in implementing computing curricula CC2001 (MRKKR, SJ, TM, MS, MA, KAF), pp. 256–260.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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