Travelled to:1 × France
1 × Germany
3 × USA
Collaborated with:T.Kim W.Kwon C.L.Liu S.Roy D.Liu D.Z.Pan S.Yoo S.Jeong S.Hong Y.Kim K.Choi J.Kong S.Eo
Talks about:perform (3) synthesi (2) arithmet (2) power (2) optim (2) subsystem (1) techniqu (1) systemat (1) platform (1) paradigm (1)
Person: Junhyung Um
DBLP: Um:Junhyung
Contributed to:
2015
2009200620022000Wrote 5 papers:
- DAC-2015-RoyLUP #multi #named #optimisation #paradigm #performance
- OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions (SR, DL, JU, DZP), p. 6.
- DATE-2009-KwonYUJ #performance #problem
- In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem (WCK, SY, JU, SWJ), pp. 1058–1063.
- DATE-2006-UmKHKCKEK #design #modelling #platform
- A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
- DAC-2002-UmK #synthesis
- Layout-aware synthesis of arithmetic circuits (JU, TK), pp. 207–212.
- DAC-2000-UmKL #fine-grained #optimisation #power management #synthesis
- A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.