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Travelled to:
1 × France
1 × USA
3 × Germany
Collaborated with:
S.Eo S.Yoo W.Kwon Y.Kim J.Kong S.Hong B.Min S.Hong C.Shin E.Chung B.Bin T.Kim J.Um T.Kim T.Kim Y.Kim
Talks about:
bus (3) architectur (2) communic (2) exploit (2) memori (2) design (2) model (2) accur (2) fast (2) chip (2)

Person: Kyu-Myung Choi

DBLP DBLP: Choi:Kyu=Myung

Contributed to:

DAC 20082008
DATE 20082008
DATE 20062006
DATE 20052005
DATE v1 20042004

Wrote 6 papers:

DAC-2008-KwonYHMCE #approach #memory management #parallel
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories (WCK, SY, SMH, BM, KMC, SKE), pp. 447–452.
DATE-2008-HongYBCEK #bias #runtime #scalability
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (SH, SY, BB, KMC, SKE, TK), pp. 242–247.
DATE-2008-KwonHYMCE #communication
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication (WCK, SMH, SY, BM, KMC, SKE), pp. 1244–1249.
DATE-2006-UmKHKCKEK #design #modelling #platform
A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.
DATE-2005-KimKKSCCKE #architecture #modelling #performance #transaction
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture (YTK, TK, YK, CS, EYC, KMC, JTK, SKE), pp. 138–139.
DATE-v1-2004-ShinKCCKE #architecture #design #performance
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design (CS, YTK, EYC, KMC, JTK, SKE), pp. 352–357.

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