Travelled to:13 × USA
2 × Germany
Collaborated with:P.Pan D.F.Wong T.Hwang T.Kim P.Saxena Y.Sun R.Libeskind-Hadas J.R.Egan K.Kim S.Kang J.Um C.Chen X.Chen S.Dong T.Gao P.M.Vaidya J.Cong B.Preas X.Yao M.Yamada Y.Liu K.Wang S.Jung
Talks about:optim (6) synthesi (4) power (4) algorithm (3) design (3) rout (3) path (3) fpga (3) cell (3) new (3)
Person: C. L. Liu
DBLP: Liu:C=_L=
Contributed to:
2001
2001200019991999199719961995199419931992199019891988198719861982Wrote 19 papers:
- DAC-2001-KimJSLK #optimisation #using
- Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique (KWK, SOJ, PS, CLL, SMK), pp. 732–737.
- DATE-2001-LiuWHL #diagrams
- Binary decision diagram with minimum expected path length (YYL, KHW, TH, CLL), pp. 708–712.
- DAC-2000-UmKL #fine-grained #optimisation #power management #synthesis
- A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis (JU, TK, CLL), pp. 98–103.
- DAC-1999-SaxenaL #using
- Crosstalk Minimization Using Wire Perturbations (PS, CLL), pp. 100–103.
- DATE-1999-KimKHL #logic #power management #synthesis
- Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
- DAC-1997-ChenHL #approach #design #power management #re-engineering
- Low Power FPGA Design — A Re-engineering Approach (CSC, TH, CLL), pp. 656–661.
- DAC-1996-ChenPL #reduction
- Desensitization for Power Reduction in Sequential Circuits (XC, PP, CLL), pp. 795–800.
- DAC-1996-PanL
- Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.
- DAC-1995-PanL
- Partial Scan with Pre-selected Scan Signals (PP, CLL), pp. 189–194.
- DAC-1994-SunL #2d #architecture
- Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture (YS, CLL), pp. 171–176.
- DAC-1993-KimL #multi #synthesis
- Utilization of Multiport Memories in Data Path Synthesis (TK, CLL), pp. 298–302.
- DAC-1993-PanDL #constraints #graph #layout #reduction
- Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.
- DAC-1992-GaoVL #algorithm #performance
- A Performance Driven Macro-Cell Placement Algorithm (TG, PMV, CLL), pp. 147–152.
- DAC-1990-CongPL #algorithm #design #modelling #standard
- General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design (JC, BP, CLL), pp. 709–715.
- DAC-1989-Libeskind-HadasL #network #problem
- Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks (RLH, CLL), pp. 400–405.
- DAC-1988-YaoYL #approach #problem
- A New Approach to the Pin Assignment Problem (XY, MY, CLL), pp. 566–572.
- DAC-1987-WongL #array #optimisation #synthesis
- Array Optimization for VLSI Synthesis (DFW, CLL), pp. 537–543.
- DAC-1986-WongL #algorithm #design
- A new algorithm for floorplan design (DFW, CLL), pp. 101–107.
- DAC-1982-EganL
- Optimal bipartite folding of PLA (JRE, CLL), pp. 141–146.