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Travelled to:
1 × Germany
Collaborated with:
W.Zhang Y.Zhu W.Yu L.Zhang R.Shi H.Peng Z.Zhu R.Murgai T.Shibuya N.Ito C.Cheng
Talks about:
network (1) voltag (1) violat (1) domain (1) worst (1) power (1) multi (1) clock (1) gate (1) find (1)

Person: Lew Chua-Eoan

DBLP DBLP: Chua-Eoan:Lew

Contributed to:

DATE 20082008

Wrote 1 papers:

DATE-2008-ZhangZYZSPZCMSIC #multi #network
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.