Travelled to:1 × Germany
1 × USA
Collaborated with:Y.Liu M.Yoshioka K.Homma Y.Kanazawa W.Zhang Y.Zhu W.Yu L.Zhang R.Shi H.Peng Z.Zhu L.Chua-Eoan R.Murgai N.Ito C.Cheng
Talks about:yield (2) simultan (1) perform (1) network (1) generat (1) voltag (1) violat (1) pareto (1) domain (1) worst (1)
Person: Toshiyuki Shibuya
DBLP: Shibuya:Toshiyuki
Contributed to:
2010
2008Wrote 2 papers:
- DAC-2010-LiuYHSK #generative #optimisation
- Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances (YL, MY, KH, TS, YK), pp. 909–912.
- DATE-2008-ZhangZYZSPZCMSIC #multi #network
- Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.