Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:P.Gaillardon G.D.Micheli M.D.Marchi S.Bobba D.Sacchetto Y.Leblebici J.Zhang
Talks about:logic (4) polar (3) bdd (3) synthesi (2) structur (2) bicondit (2) nanowir (2) control (2) effici (2) novel (2)
Person: Luca Gaetano Amarù
DBLP: Amar=ugrave=:Luca_Gaetano
Contributed to:
2014
201420132013Wrote 7 papers:
- DAC-2014-AmaruGM #algorithm #graph #logic #novel #optimisation #performance
- Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization (LGA, PEG, GDM), p. 6.
- DATE-2014-AmaruGM #diagrams #performance
- An efficient manipulation package for Biconditional Binary Decision Diagrams (LGA, PEG, GDM), pp. 1–6.
- DATE-2014-GaillardonAZM #design
- Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
- DAC-2013-AmaruGM #composition #logic #named #synthesis
- BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition (LGA, PEG, GDM), p. 6.
- DAC-2013-GaillardonMABSLM #towards #using
- Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
- DATE-2013-AmaruGM #canonical #logic #novel #synthesis
- Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
- DATE-2013-GaillardonABMSLM
- Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.