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Travelled to:
2 × France
3 × USA
Collaborated with:
G.D.Micheli M.D.Marchi Y.Leblebici J.Zhang P.Gaillardon L.G.Amarù D.Sacchetto A.Pullini D.Atienza N.Patil A.Lin H.P.Wong S.Mitra
Talks about:
nanowir (3) transistor (2) synthesi (2) polar (2) doubl (2) cnfet (2) gate (2) asic (2) imperfect (1) structur (1)

Person: Shashikanth Bobba

DBLP DBLP: Bobba:Shashikanth

Contributed to:

DAC 20132013
DATE 20132013
DAC 20122012
DAC 20102010
DATE 20092009

Wrote 5 papers:

DAC-2013-GaillardonMABSLM #towards #using
Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DAC-2012-BobbaMLM #physics #synthesis
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
DAC-2010-ZhangBPLWMM #correlation
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement (JZ, SB, NP, AL, HSPW, GDM, SM), pp. 889–892.
DATE-2009-BobbaZPAM #design #logic #standard #synthesis
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (SB, JZ, AP, DA, GDM), pp. 616–621.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.