Travelled to:1 × USA
2 × France
Collaborated with:P.Gaillardon Y.Leblebici G.D.Micheli M.D.Marchi L.G.Amarù S.Bobba X.Tang J.Sandrini M.Thammasack S.R.Omam
Talks about:nanowir (2) polar (2) asic (2) transistor (1) structur (1) monolith (1) regular (1) control (1) vertic (1) tunabl (1)
Person: Davide Sacchetto
DBLP: Sacchetto:Davide
Contributed to:
2015
20132013Wrote 3 papers:
- DATE-2015-GaillardonTSTOS #power management
- A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
- DAC-2013-GaillardonMABSLM #towards #using
- Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
- DATE-2013-GaillardonABMSLM
- Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.