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Travelled to:
1 × Germany
2 × France
3 × USA
Collaborated with:
G.D.Micheli L.G.Amarù D.Sacchetto Y.Leblebici H.G.Mohammadi M.D.Marchi S.Bobba J.Zhang M.H.B.Jamaa P.Morel J.Noël F.Clermidy I.O'Connor X.Tang J.Sandrini M.Thammasack S.R.Omam
Talks about:
polar (4) logic (4) nanowir (3) control (3) base (3) bdd (3) synthesi (2) structur (2) bicondit (2) circuit (2)

Person: Pierre-Emmanuel Gaillardon

DBLP DBLP: Gaillardon:Pierre=Emmanuel

Contributed to:

DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20112011

Wrote 10 papers:

DATE-2015-GaillardonTSTOS #power management
A ultra-low-power FPGA based on monolithically integrated RRAMs (PEG, XT, JS, MT, SRO, DS, YL, GDM), pp. 1203–1208.
DATE-2015-MohammadiGM #fault #modelling
Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
DAC-2014-AmaruGM #algorithm #graph #logic #novel #optimisation #performance
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization (LGA, PEG, GDM), p. 6.
DATE-2014-AmaruGM #diagrams #performance
An efficient manipulation package for Biconditional Binary Decision Diagrams (LGA, PEG, GDM), pp. 1–6.
DATE-2014-GaillardonAZM #design
Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
DAC-2013-AmaruGM #composition #logic #named #synthesis
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition (LGA, PEG, GDM), p. 6.
DAC-2013-GaillardonMABSLM #towards #using
Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
DATE-2013-AmaruGM #canonical #logic #novel #synthesis
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DAC-2011-GaillardonBMNCO #3d #architecture #question #towards
Can we go towards true 3-D architectures? (PEG, MHBJ, PHM, JPN, FC, IO), pp. 282–283.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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