Travelled to:4 × USA
Collaborated with:Y.Chang S.Chou V.Balabanov Z.Jiang K.Chao Y.Chen C.Huang T.Chen
Talks about:placement (4) design (3) awar (3) circuit (2) analyt (2) multilevel (1) structur (1) hierarch (1) datapath (1) routabl (1)
Person: Meng-Kai Hsu
DBLP: Hsu:Meng=Kai
Contributed to:
2013201220112009Wrote 4 papers:
- DAC-2013-HsuCHCC #design
- Routability-driven placement for hierarchical mixed-size circuit designs (MKH, YFC, CCH, TCC, YWC), p. 6.
- DAC-2012-ChouHC #design
- Structure-aware placement for datapath-intensive circuit designs (SC, MKH, YWC), pp. 762–767.
- DAC-2011-HsuCB #3d #design
- TSV-aware analytical placement for 3D IC designs (MKH, YWC, VB), pp. 664–669.
- DAC-2009-JiangHCC #multi
- Spare-cell-aware multilevel analytical placement (ZWJ, MKH, YWC, KYC), pp. 430–435.