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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
Q.Tang A.Zjajo M.Berkelaar Y.Bi K.v.d.Kolk J.F.Villena L.M.Silveira A.Nigam
Talks about:
statist (3) analysi (3) transistor (2) model (2) level (2) time (2) gate (2) base (2) uncertainti (1) manufactur (1)

Person: Nick van der Meijs

DBLP DBLP: Meijs:Nick_van_der

Contributed to:

DATE 20122012
DATE 20112011
DAC 20102010

Wrote 4 papers:

DATE-2012-TangZBM #analysis #correlation #modelling #statistics
Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.
DATE-2011-BiKVSM #analysis #performance #statistics
Fast statistical analysis of RC nets subject to manufacturing variabilities (YB, KJvdK, JFV, LMS, NvdM), pp. 31–37.
DATE-2011-NigamTZBM #nondeterminism #pseudo #representation
Pseudo circuit model for representing uncertainty in waveforms (AN, QT, AZ, MB, NvdM), pp. 1521–1524.
DAC-2010-TangZBM #analysis #simulation #statistics
RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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