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Travelled to:
2 × USA
Collaborated with:
M.Annavaram P.Reed D.Ayers V.Tiwari P.H.Wang H.Wang J.D.Collins R.Kling J.P.Shen
Talks about:
time (2) microarchitectur (1) processor (1) precomput (1) approach (1) variabl (1) itanium (1) control (1) voltag (1) variat (1)

Person: Ed Grochowski

DBLP DBLP: Grochowski:Ed

Contributed to:

HPCA 20072007
HPCA 20022002

Wrote 3 papers:

HPCA-2007-AnnavaramGR #variability
Implications of Device Timing Variability on Full Chip Timing (MA, EG, PR), pp. 37–45.
HPCA-2002-GrochowskiAT #architecture #power management #simulation
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation (EG, DA, VT), pp. 7–16.
HPCA-2002-WangWCGKS #execution #memory management
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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