Travelled to:4 × USA
Collaborated with:H.Wang P.H.Wang J.P.Shen M.D.Linderman T.H.Y.Meng E.Grochowski R.Kling G.N.Chinya H.Jiang X.Tian M.Girkar N.Y.Yang G.Lueh D.Kim B.Greene K.Chan A.B.Yunus T.Sych S.F.Moore
Talks about:multithread (2) processor (2) heterogen (2) program (2) itanium (2) system (2) multi (2) core (2) architectur (1) experiment (1)
Person: Jamison D. Collins
DBLP: Collins:Jamison_D=
Contributed to:
2008
20072004
2002Wrote 4 papers:
- ASPLOS-2008-LindermanCWM #manycore #named #programming
- Merge: a programming model for heterogeneous multi-core systems (MDL, JDC, HW, THYM), pp. 287–296.
- PLDI-2007-WangCCJTGYLW #architecture #manycore #named #parallel #programming #thread
- EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system (PHW, JDC, GNC, HJ, XT, MG, NYY, GYL, HW), pp. 156–166.
- ASPLOS-2004-WangCWKGCYSMS #framework #multi #platform #thread
- Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
- HPCA-2002-WangWCGKS #execution #memory management
- Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.