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Travelled to:
4 × USA
Collaborated with:
S.B.K.Vrudhula P.Ghanta Y.Cao R.Panda P.Wu M.D.F.Wong I.Nedelchev V.Parkhe W.Wang S.Yang R.Vattikonda F.Liu
Talks about:
circuit (3) variat (3) analysi (2) scale (2) intra (2) nano (2) die (2) systemat (1) stochast (1) sequenti (1)

Person: Sarvesh Bhardwaj

DBLP DBLP: Bhardwaj:Sarvesh

Contributed to:

DAC 20142014
DAC 20072007
DAC 20062006
DAC 20052005

Wrote 5 papers:

DAC-2014-WuWNBP #on the
On Timing Closure: Buffer Insertion for Hold-Violation Removal (PCW, MDFW, IN, SB, VP), p. 6.
DAC-2007-WangYBVVLC #performance
The Impact of NBTI on the Performance of Combinational and Sequential Circuits (WW, SY, SB, RV, SBKV, FL, YC), pp. 364–369.
DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
DAC-2006-GhantaVBP #analysis #correlation #power management #probability #scalability
Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.
DAC-2005-BhardwajV #random
Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.

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