31 papers:
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap- Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DATE-2013-ChangWB #design- Process-variation-aware Iddq diagnosis for nano-scale CMOS designs — the first step (CLC, CHPW, JB), pp. 454–457.
- DATE-2013-ChenRSIFC #analysis #process
- A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
CASE-2012-TangLY #nondeterminism #using- Tracking control of a compliant XY nano-positioner under plant uncertainty using a transfigured loop-shaping H∞ controller (HT, YL, QY), pp. 103–108.
- DATE-2012-ChenLPCPWHWM #design
- Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique (CC, WSL, RP, SC, JP, JW, RTH, HSPW, SM), pp. 1361–1366.
- DATE-2012-ZhaCL #fault #memory management #modelling #testing
- Modeling and testing of interference faults in the nano NAND Flash memory (JZ, XC, CLL), pp. 527–531.
- CASE-2011-RakotondrabeHCL #assembly #automation
- Automation of assembly and packaging at the micro/nano-scale (MR, YH, CC, PL), pp. 1–5.
- DATE-2011-HuangDEB #collaboration #communication #framework
- A circuit technology platform for medical data acquisition and communication: Outline of a collaboration project within the Swiss Nano-Tera.ch Initiative (QH, CD, CE, TB), pp. 1472–1473.
- CASE-2010-FatikowEJWNK #automation
- Automated nanorobotic handling of bio- and nano-materials (SF, VE, DJ, MWJ, FN, FK), pp. 1–6.
- DAC-2010-FujitaYLCAW #power management
- Detachable nano-carbon chip with ultra low power (SF, SY, DL, XC, DA, HSPW), pp. 631–632.
LDTA-2009-SingerBLPY10 #java- Fundamental Nano-Patterns to Characterize and Classify Java Methods (JS, GB, ML, AP, PY), pp. 191–204.
- CASE-2009-WichESF #assembly #automation
- Micro-nano-integration based on automated serial assembly (TW, CE, CS, SF), pp. 573–578.
- DAC-2009-DingZHCP #framework #integration #named #power management
- O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.
- DATE-2009-Fujita #challenge #design #question
- Nano-electronics challenge chip designers meet real nano-electronics in 2010s? (SF), pp. 431–432.
- DAC-2008-LiZY #analysis #verification
- Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification (TL, WZ, ZY), pp. 594–599.
- DATE-2008-Micheli #design
- Designing Micro/Nano Systems for a Safer and Healthier Tomorrow (GDM), p. 1.
- DATE-2008-SreedharSK #fault #modelling #on the #testing
- On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.
- DAC-2007-ZhangSJ #architecture #configuration management #design #hybrid #named #optimisation
- NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture (WZ, LS, NKJ), pp. 300–305.
- DAC-2006-BhardwajVGC #analysis #modelling #optimisation #process
- Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits (SB, SBKV, PG, YC), pp. 791–796.
- DAC-2006-Borkar
- Electronics beyond nano-scale CMOS (SB), pp. 807–808.
- DAC-2006-GhoshMKR #power management #reduction #self
- Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM (SG, SM, KK, KR), pp. 971–976.
- DATE-2006-HeJ #configuration management #framework #named #synthesis
- RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics (CH, MFJ), pp. 1179–1184.
- CASE-2005-LeeH #analysis #array #design
- An integrated system of microcantilever arrays with carbon nanotube tips for bio/nano analysis: design and control (EL, HSH), pp. 113–117.
- DAC-2005-BhardwajV #random
- Leakage minimization of nano-scale circuits in the presence of systematic and random variations (SB, SBKV), pp. 541–546.
- DAC-2005-GayasenVI
- Exploring technology alternatives for nano-scale FPGA interconnects (AG, NV, MJI), pp. 921–926.
- DATE-2005-MukhopadhyayBR #analysis #logic #modelling
- Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits (SM, SB, KR), pp. 224–229.
- DATE-2005-SukhwaniPW #design #named #statistics
- Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design (BBS, UP, JMW), pp. 758–763.
- DAC-2004-AgarwalKMR #design
- Leakage in nano-scale technologies: mechanisms, impact and design considerations (AA, CHK, SM, KR), pp. 6–11.
- DAC-2004-ZhaoBD #analysis #scalability
- A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits (CZ, XB, SD), pp. 894–899.
- DATE-v2-2004-GuptaJ #algorithm #architecture
- An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology (PG, NKJ), pp. 974–979.
FME-2002-OheimbN #hoare #logic #revisited- Hoare Logic for NanoJava: Auxiliary Variables, Side Effects, and Virtual Methods Revisited (DvO, TN), pp. 89–105.
