BibSLEIGH — Valeria

Travelled to:

1 × China
13 × USA
5 × France
5 × Germany

Collaborated with:

A.DeOrio I.Wagner T.M.Austin D.Chatterjee ∅ S.Shyam R.Parikh I.L.Markov R.Morad D.Blaauw K.Olukotun K.Constantinides S.Plaza A.Pellegrini A.Ziv F.Fummi S.Vinco B.Mammo R.Das D.Lee M.R.Kakoee L.Benini D.Fick D.Sylvester K.Chang M.Damiani S.Quer Q.Li M.Burgess J.L.Greathouse C.LeBlanc K.Aisopos L.Peh A.Nahir C.Hsu R.Gal W.Arthur R.Rodriguez A.Koyfman S.Phadke J.Hu G.K.Chen M.Mehrara M.Attariyan S.Lee S.Das T.N.Mudge N.Bombieri A.M.Kaushik H.D.Patel D.Pidan J.A.Blome B.Zhang S.A.Mahlke M.Orshansky R.Smolinski L.Chen X.Fu S.K.S.Hari J.Jiang S.V.Adve R.Galivanche A.J.Hu M.Abramovici A.Camilleri B.Bentley H.Foster S.Kapoor Mark Gallagher Lauren Biernacki Shibo Chen Zelalem Birhanu Aweke Salessawi Ferede Yitbarek Misiker Tadesse Aga A.Harris Zhixing Xu B.Kasikci S.Malik M.Tiwari

Talks about:

architectur (7) silicon (6) simul (6) base (6) design (5) acceler (4) level (4) high (4) gate (4) core (4)

Person: Valeria Bertacco

DBLP: Bertacco:Valeria

Contributed to:

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2002

1999

2019

Wrote 39 papers:

DAC-2014-ParikhDB #configuration management #power management: Power-Aware NoCs through Routing and Topology Reconfiguration (RP, RD, VB), p. 6.
DATE-2014-HsuCMGB #architecture #named #performance #validation: ArChiVED: Architectural checking via event digests for high performance validation (CHH, DC, RM, RG, VB), pp. 1–6.
DATE-2014-LeePB #configuration management: Brisk and limited-impact NoC routing reconfiguration (DL, RP, VB), pp. 1–6.
CGO-2013-ArthurMRAB #debugging #named #profiling #scalability #security: Schnauzer: scalable profiling for likely security bug sites (WA, BM, RR, TMA, VB), p. 11.
DATE-2013-BertaccoCBFVKP #on the #using: On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
DATE-2013-DeOrioLBB #debugging #detection #machine learning: Machine learning-based anomaly detection for post-silicon bug diagnosis (AD, QL, MB, VB), pp. 491–496.
DAC-2012-Bertacco: Humans for EDA and EDA for humans (VB), pp. 729–733.
DAC-2012-ChatterjeeKMZB #architecture #platform: Checking architectural outputs instruction-by-instruction on acceleration platforms (DC, AK, RM, AZ, VB), pp. 955–961.
DAC-2012-VincoCBF #architecture #gpu #named: SAGA: SystemC acceleration on GPU architectures (SV, DC, VB, FF), pp. 115–120.
DATE-2012-MammoCPNZMB #approximate #simulation: Approximating checkers for simulation acceleration (BM, DC, DP, AN, AZ, RM, VB), pp. 153–158.
DATE-2012-PellegriniSCFHJAAB #evaluation: CrashTest’ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions (AP, RS, LC, XF, SKSH, JJ, SVA, TMA, VB), pp. 1106–1109.
CGO-2011-GreathouseLAB #analysis #data flow #distributed #scalability: Highly scalable distributed dataflow analysis (JLG, CL, TMA, VB), pp. 277–288.
DAC-2011-DeOrioABP #architecture #distributed #manycore #named: DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips (AD, KA, VB, LSP), pp. 912–917.
DATE-2011-KakoeeBB #communication #named #network #reliability: ReliNoC: A reliable network for priority-based on-chip communication (MRK, VB, LB), pp. 667–672.
DAC-2010-DeOrioB #automation #design #network #social: Electronic design automation for social networks (AD, VB), pp. 621–622.
DAC-2010-NahirZGHACBFBK #validation #verification: Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.
DATE-2010-PellegriniBA #authentication: Fault-based attack of RSA authentication (AP, VB, TMA), pp. 855–860.
DAC-2009-Bertacco #debugging: Debugging strategies for mere mortals (VB), pp. 635–638.
DAC-2009-ChatterjeeDB #simulation: Event-driven gate-level simulation with GP-GPUs (DC, AD, VB), pp. 557–562.
DAC-2009-DeOrioB: Human computing for EDA (AD, VB), pp. 621–622.
DAC-2009-FickDHBBS #named #network #reliability: Vicis: a reliable network for unreliable silicon (DF, AD, JH, VB, DB, DS), pp. 812–817.
DATE-2009-ChangBM #design #using: Customizing IP cores for system-on-chip designs using extensive external don’t-cares (KHC, VB, ILM), pp. 582–585.
DATE-2009-ChatterjeeDB #named #simulation: GCS: High-performance gate-level simulation with GPGPUs (DC, AD, VB), pp. 1332–1337.
DATE-2009-FickDCBSB #algorithm #fault tolerance: A highly resilient routing algorithm for fault-tolerant NoCs (DF, AD, GKC, VB, DS, DB), pp. 21–26.
DATE-2009-WagnerB #hardware #manycore #named: Caspar: Hardware patching for multicore processors (IW, VB), pp. 658–663.
HPCA-2009-DeOrioWB #design #manycore #memory management #named #validation: Dacota: Post-silicon validation of the memory subsystem in multi-core designs (AD, IW, VB), pp. 405–416.
DATE-2008-PlazaMB #constraints #generative #random #using: Random Stimulus Generation using Entropy and XOR Constraints (SP, ILM, VB), pp. 664–669.
DATE-2008-WagnerB #adaptation #design #manycore #named #verification: MCjammer: Adaptive Verification for Multi-core Designs (IW, VB), pp. 670–675.
DATE-2007-MehraraASCBA #fault #low cost: Low-cost protection for SER upsets and silicon defects (MM, MA, SS, KC, VB, TMA), pp. 1146–1151.
DATE-2007-WagnerB #semantics #trust: Engineering trust with semantic guardians (IW, VB), pp. 743–748.
ASPLOS-2006-ShyamCPBA #fault #low cost #pipes and filters: Ultra low-cost defect protection for microprocessor pipelines (SS, KC, SP, VB, TMA), pp. 73–82.
DAC-2006-WagnerBA #design #logic: Shielding against design flaws with field repairable control logic (IW, VB, TMA), pp. 344–347.
DATE-2006-ShyamB #hybrid #verification: Distance-guided hybrid verification with GUIDO (SS, VB), pp. 1211–1216.
HPCA-2006-ConstantinidesPBZBMAO #architecture #named: BulletProof: a defect-tolerant CMP switch architecture (KC, SP, JAB, BZ, VB, SAM, TMA, MO), pp. 5–16.
DAC-2005-WagnerBA #approach #automation #generative #monitoring #named #process #testing: StressTest: an automatic approach to test generation via activity monitors (IW, VB, TMA), pp. 783–788.
DAC-2004-LeeDBABM #architecture #simulation: Circuit-aware architectural simulation (SL, SD, VB, TMA, DB, TNM), pp. 305–310.
DAC-2002-BertaccoO #performance #representation #simulation: Efficient state representation for symbolic simulation (VB, KO), pp. 99–104.
DAC-1999-BertaccoDQ #simulation: Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (VB, MD, SQ), pp. 391–396.
ASPLOS-2019-GallagherBCAYAH #architecture #named: Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn (MG, LB, SC, ZBA, SFY, MTA, AH, ZX, BK, VB, SM, MT, TMA), pp. 469–484.