Travelled to:2 × France
2 × USA
Collaborated with:∅ B.C.Paul M.Okajima T.Lee S.Yasuda D.Lee X.Chen D.Akinwande H.P.Wong H.Noguchi K.Nomura K.Abe E.Arima K.Kim T.Nakada S.Miwa H.Nakamura
Talks about:nano (3) electron (2) mram (2) chip (2) challeng (1) perform (1) circuit (1) ballist (1) analysi (1) memori (1)
Person: Shinobu Fujita
DBLP: Fujita:Shinobu
Contributed to:
2013
201020092006Wrote 4 papers:
- DATE-2013-NoguchiNAFAKNMN #energy #hybrid #memory management #performance
- D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory (HN, KN, KA, SF, EA, KK, TN, SM, HN), pp. 1813–1818.
- DAC-2010-FujitaYLCAW #power management
- Detachable nano-carbon chip with ultra low power (SF, SY, DL, XC, DA, HSPW), pp. 631–632.
- DATE-2009-Fujita #challenge #design #question
- Nano-electronics challenge chip designers meet real nano-electronics in 2010s? (SF), pp. 431–432.
- DAC-2006-PaulFOL #analysis #modelling #performance
- Modeling and analysis of circuit performance of ballistic CNFET (BCP, SF, MO, TL), pp. 717–722.