3 × USA
A.Yamada T.Sasaki A.Kawaguchi K.Takahashi T.Aoyama K.Hasegawa S.Sato T.Nakazawa K.Tomita N.Nomizu
system (3) design (2) verif (2) digit (2) larg (2) mix (2) microprogram (1) hierarch (1) support (1) simul (1)
Person: Shunichi Kato
Wrote 3 papers:
- DAC-1981-SasakiYAHKS #design #scalability #verification
- Hierarchical design verification for large digital systems (TS, AY, TA, KH, SK, SS), pp. 105–112.
- DAC-1980-SasakiYKNTN #logic #named #scalability #verification
- MIXS: A mixed level simulator for large digital system logic verification (TS, AY, SK, TN, KT, NN), pp. 626–633.
- DAC-1974-YamadaKTK #design
- Microprogramming Design support System (AY, AK, KT, SK), pp. 137–142.