Travelled to:6 × USA
Collaborated with:S.Kato ∅ N.Wakatsuki S.Funatsu S.Sato T.Aoyama T.Sasaki K.Tomita T.Fukui A.Kawaguchi K.Takahashi M.Nomura N.Takano K.Hasegawa T.Nakazawa N.Nomizu H.Shibano O.Itoh
Talks about:system (6) digit (4) larg (4) design (3) verif (3) hierarch (2) generat (2) automat (2) level (2) time (2)
Person: Akihiko Yamada
DBLP: Yamada:Akihiko
Contributed to:
198219811980197819771974Wrote 7 papers:
- DAC-1982-NomuraSTAY #verification
- Timing verification system based on delay time hierarchical nature (MN, SS, NT, TA, AY), pp. 622–628.
- DAC-1981-SasakiYAHKS #design #scalability #verification
- Hierarchical design verification for large digital systems (TS, AY, TA, KH, SK, SS), pp. 105–112.
- DAC-1981-Yamada #automation #design
- Design automation status in Japan (AY), pp. 43–50.
- DAC-1980-SasakiYKNTN #logic #named #scalability #verification
- MIXS: A mixed level simulator for large digital system logic verification (TS, AY, SK, TN, KT, NN), pp. 626–633.
- DAC-1978-YamadaWFF #automation #fault #generative #scalability #testing
- Automatic System Level Test Generation and Fault Location for Large Digital Systems (AY, NW, TF, SF), pp. 347–352.
- DAC-1977-YamadaWSITF #automation #generative #scalability #testing
- Automatic test generation for large digital circuits (AY, NW, HS, OI, KT, SF), pp. 78–83.
- DAC-1974-YamadaKTK #design
- Microprogramming Design support System (AY, AK, KT, SK), pp. 137–142.