Travelled to:1 × France
1 × Germany
1 × USA
1 × United Kingdom
Collaborated with:S.V.Adve P.Ramachandran H.Naeimi M.Li U.R.Karpuzcu A.Pellegrini R.Smolinski L.Chen X.Fu J.Jiang T.M.Austin V.Bertacco D.Gizopoulos M.Psarakis D.J.Sorin A.Meixner A.Biswas X.Vera
Talks about:fault (4) level (3) resili (2) applic (2) accur (2) microarchitectur (1) architectur (1) transient (1) processor (1) recoveri (1)
Person: Siva Kumar Sastry Hari
DBLP: Hari:Siva_Kumar_Sastry
Contributed to:
2012
20122011
2009Wrote 4 papers:
- ASPLOS-2012-HariANR #equivalence #fault #named
- Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults (SKSH, SVA, HN, PR), pp. 123–134.
- DATE-2012-PellegriniSCFHJAAB #evaluation
- CrashTest’ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions (AP, RS, LC, XF, SKSH, JJ, SVA, TMA, VB), pp. 1106–1109.
- DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online
- Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
- HPCA-2009-LiRKHA #architecture #fault #hardware #modelling
- Accurate microarchitecture-level fault modeling for studying hardware faults (MLL, PR, URK, SKSH, SVA), pp. 105–116.