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Travelled to:
1 × Germany
2 × USA
Collaborated with:
T.Lam Y.Wu W.Tang S.Deng J.Bian W.Wu Y.Zhao
Talks about:
remov (2) wire (2) procedur (1) satisfi (1) general (1) complex (1) circuit (1) solver (1) scheme (1) extend (1)

Person: Xiaoqing Yang

DBLP DBLP: Yang:Xiaoqing

Contributed to:

DATE 20122012
DAC 20102010
DAC 20072007

Wrote 3 papers:

DATE-2012-YangLTW #modelling
Almost every wire is removable: A modeling and solution for removing any circuit wire (XY, TKL, WCT, YLW), pp. 1573–1578.
DAC-2010-YangLW #complexity #fault #named
ECR: a low complexity generalized error cancellation rewiring scheme (XY, TKL, YLW), pp. 511–516.
DAC-2007-DengBWYZ #named #performance #satisfiability #using
EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure (SD, JB, WW, XY, YZ), pp. 588–593.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.