Travelled to:2 × USA
Collaborated with:S.Kajihara M.Fukunaga X.Wen T.Maeda S.Hamada Y.Ogawa T.Itoh Y.Miki T.Ishii R.Toyoshima
Talks about:interconnect (1) constraint (1) placement (1) mainfram (1) process (1) compact (1) variat (1) orient (1) design (1) toler (1)
Person: Yasuo Sato
DBLP: Sato:Yasuo
Contributed to:
20051991Wrote 2 papers:
- DAC-2005-KajiharaFWMHS #process
- Path delay test compaction with process variation tolerance (SK, MF, XW, TM, SH, YS), pp. 845–850.
- DAC-1991-OgawaIMIST #constraints #design
- Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design (YO, TI, YM, TI, YS, RT), pp. 253–258.