Travelled to:2 × France
2 × Germany
2 × USA
Collaborated with:S.Kajihara K.Miyase C.P.Ravikumar M.Hirech E.Schneider S.Holst M.A.Kochte H.Wunderlich D.Gizopoulos K.Roy P.Girard N.Nicolici M.Aso H.Furukawa Y.Yamato T.Suzuki Y.Ohsumi K.K.Saluja M.Fukunaga T.Maeda S.Hamada Y.Sato B.Cheon E.Lee L.Wang P.Hsu J.Cho J.Park H.Chao S.Wu
Talks about:test (6) speed (3) power (3) strategi (2) devic (2) delay (2) scan (2) path (2) awar (2) low (2)
Person: Xiaoqing Wen
DBLP: Wen:Xiaoqing
Contributed to:
201520112008
200720052005Wrote 7 papers:
- DATE-2015-SchneiderHKWW #fault #simulation
- GPU-accelerated small delay fault simulation (ES, SH, MAK, XW, HJW), pp. 1174–1179.
- DATE-2011-MiyaseWAFYK #generative #testing
- Transition-Time-Relation based capture-safety checking for at-speed scan test generation (KM, XW, MA, HF, YY, SK), pp. 895–898.
- DATE-2008-GizopoulosRGNW #power management #testing
- Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
- DATE-2008-RavikumarHW #power management
- Test Strategies for Low Power Devices (CPR, MH, XW), pp. 728–733.
- DAC-2007-WenMSKOS #effectiveness #reduction #testing
- Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing (XW, KM, TS, SK, YO, KKS), pp. 527–532.
- DAC-2005-KajiharaFWMHS #process
- Path delay test compaction with process variation tolerance (SK, MF, XW, TM, SH, YS), pp. 845–850.
- DATE-2005-CheonLWWHCPCW #logic
- At-Speed Logic BIST for IP Cores (BC, EL, LTW, XW, PH, JC, JP, HC, SW), pp. 860–861.