Travelled to:1 × Germany
2 × France
Collaborated with:J.Xu X.Wu Z.Wang X.Wang M.Nikdast L.H.K.Duong P.Yang Z.Wang K.J.Chen W.Zhang Y.Ye Y.Thonnart S.L.Beux H.Li R.K.V.Maeda
Talks about:power (5) nois (3) ground (2) induc (2) gate (2) chip (2) interconnect (1) processor (1) crosstalk (1) character (1)
Person: Zhehui Wang
DBLP: Wang:Zhehui
Contributed to:
201520142013Wrote 4 papers:
- DATE-2015-DuongNXWTBYWW #analysis
- Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
- DATE-2015-WangWXWWYDLMW #adaptation #process
- Adaptively tolerate power-gating-induced power/ground noise under process variations (ZW, XW, JX, XW, ZW, PY, LHKD, HL, RKVM, ZW), pp. 483–488.
- DATE-2014-WangXWCWW #manycore #power management
- Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
- DATE-2013-WangXZWYWNW #using
- Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.