Travelled to:1 × USA
2 × France
2 × Germany
Collaborated with:R.Hersemeule S.L.Beux P.Vivet F.Clermidy H.Li I.O'Connor S.Foroutan A.Jerraya N.Coste H.Garavel H.Hermanns M.Zidouni L.H.K.Duong M.Nikdast J.Xu Z.Wang P.Yang X.Wu Z.Wang E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist S.Bernard G.Moritz O.Billoint Y.Maneglia P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:interconnect (2) design (2) optic (2) fulli (2) evalu (2) chip (2) multiprocessor (1) complementari (1) multithread (1) architectur (1)
Person: Yvain Thonnart
DBLP: Thonnart:Yvain
Contributed to:
2015
2015201320102008Wrote 6 papers:
- DAC-2015-LiBTO #communication #energy #performance
- Complementary communication path for energy efficient on-chip optical interconnects (HL, SLB, YT, IO), p. 6.
- DATE-2015-DuongNXWTBYWW #analysis
- Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
- DATE-2010-ForoutanTHJ #performance
- An analytical method for evaluating Network-on-Chip performance (SF, YT, RH, AJ), pp. 1629–1632.
- DATE-2010-ThonnartVC #framework #integration #power management
- A fully-asynchronous low-power framework for GALS NoC integration (YT, PV, FC), pp. 33–38.
- DATE-2008-CosteGHHTZ #architecture #design #embedded #evaluation #parallel #thread #validation
- Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures (NC, HG, HH, RH, YT, MZ), pp. 88–89.