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Travelled to:
1 × Germany
1 × USA
4 × France
Collaborated with:
X.Wu W.Zhang Z.Wang X.Wang Z.Wang M.Nikdast H.Gu Y.Ye L.H.K.Duong P.Yang Z.Wang W.Wolf J.Henkel S.T.Chakradhar T.Lv K.J.Chen Y.Thonnart S.L.Beux Y.Xie Q.Li W.Liu H.Li R.K.V.Maeda
Talks about:
power (6) chip (6) nois (4) network (3) optic (3) crosstalk (2) system (2) ground (2) induc (2) gate (2)

Person: Jiang Xu


Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DAC 20102010
DATE 20092009
DATE v2 20042004

Wrote 7 papers:

DATE-2015-DuongNXWTBYWW #analysis
Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
DATE-2015-WangWXWWYDLMW #adaptation #process
Adaptively tolerate power-gating-induced power/ground noise under process variations (ZW, XW, JX, XW, ZW, PY, LHKD, HL, RKVM, ZW), pp. 483–488.
DATE-2014-WangXWCWW #manycore #power management
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATE-2013-WangXZWYWNW #using
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.
DAC-2010-XieNXZLWYWL #analysis #fault
Crosstalk noise and bit error rate analysis for optical network-on-chip (YX, MN, JX, WZ, QL, XW, YY, XW, WL), pp. 657–660.
DATE-2009-GuXZ #multi #power management
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip (HG, JX, WZ), pp. 3–8.
DATE-v2-2004-XuWHCL #case study #design #embedded #video
A Case Study in Networks-on-Chip Design for Embedded Video (JX, WW, JH, STC, TL), pp. 770–777.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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