15 papers:
DATE-2015-GoudVRR #design #robust #symmetry- Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
- DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using
- Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
- DATE-2015-ShutoYS #architecture #case study #comparative #using
- Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (YS, SY, SS), pp. 866–871.
DAC-2014-KiamehrOTN #analysis #approach #fault- Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach (SK, THO, MBT, SRN), p. 6.
- DATE-2014-DuW #optimisation #process #standard
- Optimization of standard cell based detailed placement for 16 nm FinFET process (YD, MDFW), pp. 1–6.
- DATE-2014-KhanAHKKRC #analysis #bias
- Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.
- DAC-2013-KleebergerGS #evaluation #modelling #performance #predict #standard
- Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies (VK, HEG, US), p. 6.
- DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
- TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
- DAC-2012-SinhaYCCC #design #modelling #predict
- Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
- DAC-2011-LeeJ #framework #modelling #named #process
- CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations (CYL, NKJ), pp. 866–871.
CASE-2010-SetoL #adaptation- On-board AUV autonomy through adaptive fins control (MLS, HL), pp. 933–939.
- DATE-2010-MishraJ #optimisation #power management #synthesis #using
- Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
ICPR-2008-StewmanD #recognition- Contour registration and corresponding point selection for dorsal fin recognition (JHS, KD), pp. 1–5.
ICEIS-AIDSS-2007-AlevizosKPSB #fuzzy #information retrieval #multi- Fuzzy Interval Number (FIN) Techniques for Multilingual and Cross Language Information Retrieval (TA, VGK, SEP, CS, PB), pp. 348–355.
- ICEIS-AIDSS-2006-MarinagiAKS #fuzzy #information retrieval
- Fuzzy Interval Number (FIN) Techniques for Cross Language Information Retrieval (CM, TA, VGK, CS), pp. 249–256.
