25 papers:
DATE-2015-GoudVRR #design #robust #symmetry- Asymmetric underlapped FinFET based robust SRAM design at 7nm node (AAG, RV, AR, KR), pp. 659–664.
- DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using
- Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
- DATE-2015-SharmaGR
- Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems (AS, AAG, KR), pp. 1443–1448.
- DATE-2015-ShutoYS #architecture #case study #comparative #using
- Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (YS, SY, SS), pp. 866–871.
DAC-2014-KiamehrOTN #analysis #approach #fault- Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach (SK, THO, MBT, SRN), p. 6.
- DATE-2014-DuW #optimisation #process #standard
- Optimization of standard cell based detailed placement for 16 nm FinFET process (YD, MDFW), pp. 1–6.
- DATE-2014-GaillardonAZM #design
- Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
- DATE-2014-KhanAHKKRC #analysis #bias
- Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.
- DATE-2014-TrivediAM #power management
- Ultra-low power electronics with Si/Ge tunnel FET (ART, MFA, SM), pp. 1–6.
- DAC-2013-KleebergerGS #evaluation #modelling #performance #predict #standard
- Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies (VK, HEG, US), p. 6.
- DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named
- TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
- DAC-2013-TrivediCM #case study #power management
- Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier (ART, SC, SM), p. 6.
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
- DATE-2013-GaillardonABMSLM
- Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
- DAC-2012-SinhaYCCC #design #modelling #predict
- Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
- DAC-2011-LeeJ #framework #modelling #named #process
- CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations (CYL, NKJ), pp. 866–871.
- DATE-2010-MishraJ #optimisation #power management #synthesis #using
- Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
- DAC-2009-PatilLZWM #logic #using
- Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions (NP, AL, JZ, HSPW, SM), pp. 304–309.
- DAC-2008-BrockmanLKKM #array #design #memory management #multi #programmable #using
- Design of a mask-programmable memory/multiplier array using G4-FET technology (JBB, SL, PMK, AK, MMM), pp. 337–338.
- DAC-2008-ChoudhuryYGM
- Technology exploration for graphene nanoribbon FETs (MRC, YY, JG, KM), pp. 272–277.
- DAC-2008-KshirsagarEB #analysis #performance
- Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs (CK, MNEZ, KB), pp. 250–255.
- DATE-2007-HashempourL #detection #fault #modelling
- Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs (HH, FL), pp. 841–846.
- DAC-1993-VisweswariahW #incremental #simulation
- Incremental Event-Driven Simulation of Digital FET Circuits (CV, JAW), pp. 737–741.
- DAC-1979-HsiehR #functional #latency #megamodelling
- Macrosimulation with Quasi-general Symbolic FET Macromodel and Functional Latency (HYH, NBR), pp. 229–234.
- DAC-1979-LallierJ
- A new circuit placement program for FET chips (KWL, RKJ), pp. 109–113.
