35 papers:
DAC-2015-HanKL #design #evaluation #using- Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router (KH, ABK, HL), p. 6.
- DAC-2015-KhdrPSH #resource management
- Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips (HK, SP, MS, JH), p. 6.
ICLP-2015-LiVPSB #debugging #using- Debugging ASP using ILP (TL, MDV, JP, KS, TB).
DATE-2013-RutzigBC #configuration management #energy #framework #multi- A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation (MBR, ACSB, LC), pp. 1559–1564.
CAV-2013-ManoliosP #modulo theories- ILP Modulo Theories (PM, VP), pp. 662–677.
ASPLOS-2012-ParkSPCM #architecture #performance- SIMD defragmenter: efficient ILP realization on data-parallel architectures (YP, SS, HP, HKC, SAM), pp. 363–374.
- DAC-2009-LinC #design
- ILP-based pin-count aware design methodology for microfluidic biochips (CCYL, YWC), pp. 258–263.
- DATE-2009-FytrakiP #configuration management
- ReSim, a trace-driven, reconfigurable ILP processor simulator (SF, DNP), pp. 536–541.
- DATE-2009-YiHZEA #architecture #manycore #scheduling
- An ILP formulation for task mapping and scheduling on multi-core architectures (YY, WH, XZ, ATE, TA), pp. 33–38.
SAC-2009-Manine #information management #learning #multi #ontology- Learning the ontological theory of an information extraction system in the multi-predicate ILP setting (APM), pp. 1578–1582.
- DAC-2008-YuhSYC #algorithm
- A progressive-ILP based routing algorithm for cross-referencing biochips (PHY, SSS, CLY, YWC), pp. 284–289.
FASE-2008-AlrajehRU #behaviour #modelling #using- Deriving Non-zeno Behavior Models from Goal Models Using ILP (DA, AR, SU), pp. 1–15.
SEKE-2008-ChenZX #approach #reduction #testing- A Degraded ILP Approach for Test Suite Reduction (ZC, XZ, BX), pp. 494–499.
- ICLP-2008-MuggletonST #bias #declarative #logic programming #named #using
- TopLog: ILP Using a Logic Program Declarative Bias (SM, JCAS, ATN), pp. 687–692.
- ICLP-2008-Santos #bias #declarative #logic programming #named #using
- TopLog: ILP Using a Logic Program Declarative Bias (JCAS), pp. 818–819.
- DATE-2007-OstlerC #architecture #network
- An ILP formulation for system-level application mapping on network processor architectures (CO, KSC), pp. 99–104.
- DAC-2006-ChoP #named
- BoxRouter: a new global router based on box expansion and progressive ILP (MC, DZP), pp. 373–378.
- DAC-2005-BeckC #configuration management
- Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility (ACSB, LC), pp. 732–737.
CGO-2004-Winkel #performance #scheduling- Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling (SW), pp. 189–200.
VMCAI-2004-Wilhelm #why- Why AI + ILP Is Good for WCET, but MC Is Not, Nor ILP Alone (RW), pp. 309–322.
- DATE-2003-PillaiJ #clustering #scheduling
- Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling (SP, MFJ), pp. 10422–10427.
HPCA-2003-TaylorLAA #architecture #network- Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture (MBT, WL, SPA, AA), pp. 341–353.
- ICLP-2003-Ramirez
- Inducing Musical Rules with ILP (RR), pp. 502–504.
- DAC-2002-KoushanfarWFP
- ILP-based engineering change (FK, JLW, JF, MP), pp. 910–915.
- CAV-2002-ClarkeGKS #abstraction #machine learning #satisfiability #using
- SAT Based Abstraction-Refinement Using ILP and Machine Learning Techniques (EMC, AG, JHK, OS), pp. 265–279.
- HPCA-2001-KailasEA #clustering #code generation #framework #named
- CARS: A New Code Generation Framework for Clustered ILP Processors (KK, KE, AKA), pp. 133–143.
LCTES-OM-2001-KastnerW #scheduling- ILP-based Instruction Scheduling for IA-64 (DK, SW), pp. 145–154.
- CL-2000-Page #named
- ILP: Just Do It (DP), pp. 25–40.
- DAC-1999-KimHT #on the #self #synthesis
- On ILP Formulations for Built-In Self-Testable Data Path Synthesis (HBK, DSH, TT), pp. 742–747.
- HPCA-1999-DurbhakulaPA #multi #simulation #trade-off
- Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors (MD, VSP, SVA), pp. 23–32.
- ASPLOS-1998-RanganathanF #distributed #empirical #execution #modelling
- An Empirical Study of Decentralized ILP Execution Models (NR, MF), pp. 272–281.
- EDTC-1997-MignotteP #scheduling #using
- Scheduling using mixed arithmetic: an ILP formulation (AM, OP), p. 621.
CADE-1997-DahnGHW #automation #integration #interactive #proving #theorem proving- Integration of Automated and Interactive Theorem Proving in ILP (BID, JG, TH, AW), pp. 57–60.
- ASPLOS-1996-PaiRAH #consistency #evaluation #memory management #modelling
- An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors (VSP, PR, SVA, TH), pp. 12–23.
- DAC-1995-DeCastelo-Vide-e-SouzaPP #algorithm #approach #architecture #optimisation #throughput #using
- Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming (YGDVeS, MP, ACP), pp. 113–118.
