Travelled to:3 × France
9 × USA
Collaborated with:G.G.d.Jong ∅ H.D.Man A.B.Kahng S.Vercauteren S.Nath C.Ykman-Couvreur E.Verlind T.Kolks S.Yan X.Zhu A.R.Newton P.Vanbekbergen M.H.Sawasaki J.C.Monteiro S.Devadas O.Coudert J.C.Madre K.Samadi R.S.Ramanujam D.Verkest A.Kondratyev M.Kishinevsky A.Yakovlev
Talks about:circuit (5) effici (5) asynchron (4) applic (4) time (4) architectur (3) concurr (3) system (3) specif (3) design (3)
Person: Bill Lin
DBLP: Lin:Bill
Contributed to:
2013
20122010
2007199919981998199619951994199419921987Wrote 21 papers:
- DATE-2013-KahngLN #design #estimation #metamodelling #problem
- Enhanced metamodeling techniques for high-dimensional IC design estimation problems (ABK, BL, SN), pp. 1861–1866.
- DAC-2012-KahngLN #estimation #modelling
- Explicit modeling of control and data for improved NoC router estimation (ABK, BL, SN), pp. 392–397.
- DAC-2010-KahngLSR #optimisation
- Trace-driven optimization of networks-on-chip configurations (ABK, BL, KS, RSR), pp. 437–442.
- LCTES-2007-YanL #architecture #clustering #execution
- Stream execution on wide-issue clustered VLIW architectures (SY, BL), pp. 158–160.
- DAC-1999-ZhuL #compilation #configuration management #hardware
- Hardware Compilation for FPGA-Based Configurable Computing Machines (XZ, BL), pp. 697–702.
- DAC-1998-Lin #concurrent #source code #synthesis
- Software Synthesis of Process-Based Concurrent Programs (BL), pp. 502–505.
- DATE-1998-Lin #compilation #concurrent #performance #runtime #scheduling #source code
- Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling (BL), pp. 211–217.
- DATE-1998-VercauterenVJL #analysis #partial order #performance #using #verification
- Efficient Verification using Generalized Partial Order Analysis (SV, DV, GGdJ, BL), pp. 782–789.
- DAC-1996-Lin #design #hardware #network
- A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network Applications (BL), pp. 672–677.
- DAC-1996-VercauterenLM #architecture #embedded
- Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications (SV, BL, HDM), pp. 521–526.
- DAC-1996-VercauterenLM96a #architecture #embedded #kernel #realtime
- A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures (SV, BL, HDM), pp. 678–683.
- DAC-1996-VerlindJL #analysis #performance
- Efficient Partial Enumeration for Timing Analysis of Asynchronous Systems (EV, GGdJ, BL), pp. 55–58.
- DAC-1995-LinJK #optimisation
- Hierarchical Optimization of Asynchronous Circuits (BL, GGdJ, TK), pp. 712–717.
- DAC-1995-SawasakiYL #implementation
- Externally Hazard-Free Implementations of Asynchronous Circuits (MHS, CYC, BL), pp. 718–724.
- DAC-1994-JongL #communication #concurrent #design #petri net
- A Communicating Petri Net Model for the Design of Concurrent Asynchronous Modules (GGdJ, BL), pp. 49–55.
- DAC-1994-KondratyevKLVY #implementation #independence
- Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.
- DAC-1994-MonteiroDL #estimation #logic #performance #process
- A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits (JCM, SD, BL), pp. 12–17.
- DAC-1994-VerlindKJLM #abstraction #communication #performance #verification
- A Time Abstraction Method for Efficient Verification of Communicating Systems (EV, TK, GGdJ, BL, HDM), pp. 609–614.
- EDAC-1994-VanbekbergenYLM #graph #interface #specification
- A Generalized Signal Transition Graph Model for Specification of Complex Interfaces (PV, CYC, BL, HDM), pp. 378–384.
- DAC-1992-LinCM #generative #multi
- Symbolic Prime Generation for Multiple-Valued Functions (BL, OC, JCM), pp. 40–44.
- DAC-1987-LinN #named
- KAHLUA: A Hierarchical Circuit Disassembler (BL, ARN), pp. 311–317.