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Travelled to:
1 × Canada
1 × USA
4 × France
5 × Germany
Collaborated with:
J.Mathew C.Liu A.M.Jabir S.Subbarayan R.A.Shafik J.Singh Z.Link K.Chakrabarty S.M.Reddy W.Kunz M.Hosseinabady M.R.Kakoee S.Banerjee R.K.Roy S.T.Chakradhar L.Sun Z.Li Y.Yang M.Ottavi S.Pontarelli X.Huang S.Bhattacharjee A.J.Ricketts K.Ramakrishnan N.Vijaykrishnan S.Hollis S.P.Mohanty
Talks about:
power (4) test (4) low (3) switch (2) novel (2) graph (2) sram (2) base (2) complementari (1) architectur (1)

Person: Dhiraj K. Pradhan

DBLP DBLP: Pradhan:Dhiraj_K=

Contributed to:

DATE 20142014
DATE 20132013
DATE 20102010
DATE 20092009
DATE 20082008
DATE 20062006
DATE v2 20042004
SAT 20042005
DATE 20032003
DAC 19951995
EDAC-ETC-EUROASIC 19941994

Wrote 12 papers:

DATE-2014-SunMSPL #design #power management #robust
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance (LS, JM, RAS, DKP, ZL), pp. 1–4.
DATE-2014-YangMPOP #logic #using
Complementary resistive switch based stateful logic operations using material implication (YY, JM, DKP, MO, SP), pp. 1–4.
DATE-2013-HuangMSBP #effectiveness #performance
A fast and Effective DFT for test and diagnosis of power switches in SoCs (XH, JM, RAS, SB, DKP), pp. 1089–1092.
DATE-2010-RickettsSRVP #power management
Investigating the impact of NBTI on different power saving cache strategies (AJR, JS, KR, NV, DKP), pp. 592–597.
DATE-2009-SinghPHMM #embedded #power management
Single ended 6T SRAM with isolated read-port for low-power embedded systems (JS, DKP, SH, SPM, JM), pp. 917–922.
DATE-2008-HosseinabadyKMP #architecture #energy #graph #latency #performance #scalability
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs (MH, MRK, JM, DKP), pp. 1370–1373.
DATE-2006-LiuLP #scheduling
Reuse-based test access and integrated test scheduling for network-on-chip (CL, ZL, DKP), pp. 303–308.
DATE-v2-2004-JabirP #diagrams #multi #named #representation
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions (AMJ, DKP), pp. 1388–1389.
SAT-J-2004-SubbarayanP05 #named #preprocessor #satisfiability
NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances (SS, DKP), pp. 276–291.
DATE-2003-PradhanLC #detection #fault #generative #named #novel
EBIST: A Novel Test Generator with Built-In Fault Detection Capability (DKP, CL, KC), pp. 10224–10229.
DAC-1995-ReddyKP #framework #novel #synthesis #verification
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (SMR, WK, DKP), pp. 414–419.
EDAC-1994-BanerjeeRCP #graph transformation
Signal Transition Graph Transformations for Initializability (SB, RKR, STC, DKP), p. 670.

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