Travelled to:2 × Germany
4 × France
4 × USA
Collaborated with:C.Ababei N.Saraf H.Mogal W.Choi P.Maidee J.Chen J.Moon S.Ogrenci M.Sarrafzadeh Z.Wang A.Scheel D.J.Lilja M.D.Riedel H.Safizadeh M.Tahghighi E.K.Ardestani G.Tavasoli A.Yazdanbakhsh D.Mahajan B.Thwaites J.Park A.Nagendrakumar S.Sethuraman K.Ramkrishnan N.Ravindran R.Jariwala A.Rahimi H.Esmaeilzadeh
Talks about:use (3) reconfigur (2) stochast (2) circuit (2) random (2) partit (2) driven (2) design (2) simul (2) time (2)
Person: Kia Bazargan
DBLP: Bazargan:Kia
Contributed to:
2015
201520142009200720032003200220022001Wrote 10 papers:
- DAC-2015-WangSBS #feedback #implementation #probability
- Randomness meets feedback: stochastic implementation of logistic map dynamical system (ZW, NS, KB, AS), p. 7.
- DATE-2015-YazdanbakhshMTP #approximate #design #hardware #named
- Axilog: language support for approximate hardware design (AY, DM, BT, JP, AN, SS, KR, NR, RJ, AR, HE, KB), pp. 812–817.
- DATE-2014-SarafBLR #probability #using
- IIR filters using stochastic arithmetic (NS, KB, DJL, MDR), pp. 1–6.
- DATE-2009-SafizadehTATB #nondeterminism #using
- Using randomization to cope with circuit uncertainty (HS, MT, EKA, GT, KB), pp. 815–820.
- DATE-2007-MogalB #architecture #reduction
- Microarchitecture floorplanning for sub-threshold leakage reduction (HM, KB), pp. 1238–1243.
- DAC-2003-MaideeAB #clustering #performance
- Fast timing-driven partitioning-based placement for island style FPGAs (PM, CA, KB), pp. 598–603.
- DATE-2003-ChoiB #migration #network #using
- Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration (WC, KB), pp. 11104–11105.
- DAC-2002-ChenMB #configuration management #generative
- A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator (JC, JM, KB), pp. 349–354.
- DATE-2002-AbabeiB #clustering #statistics
- Statistical Timing Driven Partitioning for VLSI Circuits (CA, KB), p. 1109.
- DAC-2001-BazarganOS #architecture #compilation #configuration management #design #physics #scheduling
- Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures (KB, SO, MS), pp. 635–640.