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Travelled to:
1 × Germany
2 × France
3 × USA
Collaborated with:
G.Wei D.M.Brooks V.J.Reddi M.D.Smith G.H.Holloway W.Kim K.K.Rangan J.L.Oatley R.Joseph S.Campanoni P.Bose A.Buyuktosunoglu J.A.Darringer M.B.Healy H.M.Jacobson I.Nair J.A.Rivers J.Shin A.Vega A.J.Weger
Talks about:
voltag (3) chip (3) use (3) processor (2) challeng (2) softwar (2) reduc (2) power (2) level (2) nois (2)

Person: Meeta Sharma Gupta

DBLP DBLP: Gupta:Meeta_Sharma

Contributed to:

DATE 20122012
DAC 20092009
DATE 20092009
HPCA 20092009
HPCA 20082008
DATE 20072007

Wrote 7 papers:

DATE-2012-BoseBDGHJNRSVW #challenge #manycore #power management
Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DATE-2009-GuptaRHWB #approach
An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
HPCA-2009-ReddiGHWSB #predict #using
Voltage emergency prediction: Using signatures to reduce operating margins (VJR, MSG, GHH, GYW, MDS, DMB), pp. 18–29.
HPCA-2008-GuptaRSWB #commit #induction #named
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (MSG, KKR, MDS, GYW, DMB), pp. 381–392.
HPCA-2008-KimGWB #analysis #performance #using
System level analysis of fast, per-core DVFS using on-chip switching regulators (WK, MSG, GYW, DMB), pp. 123–134.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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