Travelled to:2 × Germany
5 × France
8 × USA
Collaborated with:C.A.Papachristou A.Attarha J.Carletta M.H.Tehranipour J.Chin K.Chakrabarty N.Ahmed C.Lucas F.Martin M.Spining H.Harmanani
Talks about:test (8) control (5) integr (5) use (5) synthesi (4) datapath (4) fault (4) base (4) schedul (3) analysi (3)
Person: Mehrdad Nourani
DBLP: Nourani:Mehrdad
Contributed to:
200420042003
200220012000200019991999199819971997199619931992Wrote 17 papers:
- DATE-v1-2004-ChinN #scheduling #trade-off
- SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance (JC, MN), pp. 710–711.
- DATE-v2-2004-TehranipourNC #flexibility #testing
- Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression (MHT, MN, KC), pp. 1284–1289.
- DATE-2003-AhmedTN #testing
- Extending JTAG for Testing Signal Integrity in SoCs (NA, MHT, MN), pp. 10218–10223.
- DAC-2002-AttarhaN #analysis #fault #modelling #using
- Signal integrity fault analysis using reduced-order modeling (AA, MN), pp. 367–370.
- DAC-2001-NouraniA #self
- Built-In Self-Test for Signal Integrity (MN, AA), pp. 792–797.
- DAC-2000-AttarhaNL #fault #fuzzy #logic #modelling #simulation #using
- Modeling and simulation of real defects using fuzzy logic (AA, MN, CL), pp. 631–636.
- DAC-2000-NouraniCP
- Synthesis-for-testability of controller-datapath pairs that use gated clocks (MN, JC, CAP), pp. 613–618.
- DATE-2000-CarlettaPN #analysis #detection #fault #using
- Detecting Undetectable Controller Faults Using Power Analysis (JC, CAP, MN), pp. 723–728.
- DAC-1999-PapachristouMN #testing
- Microprocessor Based Testing for Core-Based System on Chip (CAP, FM, MN), pp. 586–591.
- DATE-1999-CarlettaNP #synthesis #testing
- Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs (JC, MN, CAP), pp. 278–282.
- DATE-1998-NouraniP #fault #testing
- A Bypass Scheme for Core-Based System Fault Testing (MN, CAP), pp. 979–980.
- DAC-1997-NouraniCP #fault #testing
- A Scheme for Integrated Controller-Datapath Fault Testing (MN, JC, CAP), pp. 546–551.
- EDTC-1997-NouraniP #analysis #behaviour #using
- Structural BIST insertion using behavioral test analysis (MN, CAP), pp. 64–68.
- DAC-1996-PapachristouSN #design #effectiveness #multi #power management
- An Effective Power Management Scheme for RTL Design Based on Multiple Clocks (CAP, MS, MN), pp. 337–342.
- DAC-1993-NouraniP #algorithm #estimation #layout
- A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.
- DAC-1993-PapachristouHN #approach #synthesis
- An Approach for Redesigning in Data Path Synthesis (CAP, HH, MN), pp. 419–423.
- DAC-1992-NouraniP #automation #scheduling #synthesis
- Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems (MN, CAP), pp. 99–105.