Travelled to:1 × Sweden
3 × Germany
4 × France
7 × USA
Collaborated with:∅ L.Wehmeyer H.Falk R.Leupers D.Cordes M.Lorenz R.Niemann U.Bieker M.Balakrishnan L.Nowak M.Verma A.Basu S.Plazar J.C.Kleinsorge R.Pyka F.Klein S.Mamagkakis P.Lokuciejewski S.Steinke B.Lee
Talks about:system (6) program (5) generat (5) code (5) softwar (4) design (4) awar (4) processor (3) algorithm (3) synthesi (3)
Person: Peter Marwedel
DBLP: Marwedel:Peter
Facilitated 1 volumes:
EdContributed to:
2012
20122010200920052004200320021998
1997199719951989198619841979Wrote 19 papers:
- CGO-2012-PlazarKMF
- WCET-aware static locking of instruction caches (SP, JCK, PM, HF), pp. 44–52.
- DATE-2012-CordesM #algorithm #parallel #search-based #using
- Multi-objective aware extraction of task-level parallelism using genetic algorithms (DC, PM), pp. 394–399.
- LCTES-2010-PykaKMM #approach #embedded #framework #platform
- Versatile system-level memory-aware platform description approach for embedded MPSoCs (RP, FK, PM, SM), pp. 9–16.
- CGO-2009-CordesFM #abstract interpretation #analysis #modelling #performance #precise #slicing
- A Fast and Precise Static Loop Analysis Based on Abstract Interpretation, Program Slicing and Polytope Models (PL, DC, HF, PM), pp. 136–146.
- DATE-2005-WehmeyerM #embedded #memory management #predict
- nfluence of Memory Hierarchies on Predictability for Time Constrained Embedded Software (LW, PM), pp. 600–605.
- DATE-v2-2004-LorenzM #algorithm #code generation #search-based #using
- Phase Coupled Code Generation for DSPs Using a Genetic Algorithm (ML, PM), pp. 1270–1275.
- DATE-v2-2004-VermaWM #algorithm
- Cache-Aware Scratchpad Allocation Algorithm (MV, LW, PM), pp. 1264–1269.
- DATE-2003-FalkM #control flow #source code
- Control Flow Driven Splitting of Loop Nests at the Source Code Level (HF, PM), pp. 10410–10415.
- DATE-2002-SteinkeWLM #energy #reduction
- Assigning Program and Data Objects to Scratchpad for Energy Reduction (SS, LW, BSL, PM), pp. 409–415.
- DATE-1998-BasuLM #source code
- Register-Constrained Address Computation in DSP Programs (AB, RL, PM), pp. 929–930.
- DATE-1998-NiemannM #communication #concurrent #hardware #synthesis
- Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems (RN, PM), pp. 912–913.
- DAC-1997-Marwedel #code generation
- Code Generation for Core Processors (PM), pp. 232–237.
- EDTC-1997-LeupersM #generative #modelling
- Retargetable generation of code selectors from HDL processor models (RL, PM), pp. 140–144.
- DAC-1995-BiekerM #constraints #generative #logic programming #self #using
- Retargetable Self-Test Program Generation Using Constraint Logic Programming (UB, PM), pp. 605–611.
- DAC-1989-BalakrishnanM #approach #design #scheduling #synthesis
- Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration (MB, PM), pp. 68–74.
- DAC-1989-NowakM #code generation #hardware #verification
- Verification of Hardware Descriptions by Retargetable Code Generation (LN, PM), pp. 441–447.
- DAC-1986-Marwedel #synthesis
- A new synthesis for the MIMOLA software system (PM), pp. 271–277.
- DAC-1984-Marwedel #design #tool support
- The mimola design system: Tools for the design of digital processors (PM), pp. 587–593.
- DAC-1979-Marwedel #design
- The MIMOLA design system: Detailed description of the software system (PM), pp. 59–63.