BibSLEIGH — Seda_Ogrenci

Travelled to:

1 × Germany
4 × France
7 × USA

Collaborated with:

J.Long G.Memik M.Ni R.Mukherjee A.A.D.Barrio R.Hermida M.C.Molina S.Liu J.M.Mendias M.Grayson B.Egilmez O.Ergin Y.Zhang R.Jafari E.Kursun J.M.Mendías G.Tziantzioulis A.M.Gok S.M.Faisal N.Hardavellas S.Parthasarathy B.Leung A.Neckar N.Hardavellas

Talks about:

awar (6) temperatur (5) optim (5) synthesi (4) power (4) level (4) high (3) thermoelectr (2) thermal (2) schedul (2)

Person: Seda Ogrenci Memik

DBLP: Memik:Seda_Ogrenci

Contributed to:

2015

2013

2011

2010

2008

2007

2006

2005

2003

Wrote 17 papers:

DAC-2015-TziantzioulisGF #correlation #fault #float #integer #named: b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units (GT, AMG, SMF, NH, SOM, SP), p. 6.
DATE-2015-EgilmezMME #smarttech: User-specific skin temperature-aware DVFS for smartphones (BE, GM, SOM, OE), pp. 1217–1220.
DATE-2013-BarrioHMMM #multi #synthesis: Multispeculative additive trees in high-level synthesis (AADB, RH, SOM, JMM, MCM), pp. 188–193.
DATE-2011-BarrioMMMH #optimisation: Power optimization in heterogenous datapaths (AADB, SOM, MCM, JMM, RH), pp. 1400–1405.
HPCA-2011-LiuLNMMH #hardware: Hardware/software techniques for DRAM thermal management (SL, BL, AN, SOM, GM, NH), pp. 515–525.
DAC-2010-LongM #framework #optimisation: A framework for optimizing thermoelectric active cooling systems (JL, SOM), pp. 591–596.
DATE-2010-BarrioMMHM #functional #synthesis #using: Using Speculative Functional Units in high level synthesis (AADB, MCM, JMM, RH, SOM), pp. 1779–1784.
DATE-2010-LongM #bias #monitoring #network #optimisation: Optimization of the bias current network for accurate on-chip thermal monitoring (JL, SOM), pp. 1365–1368.
DATE-2010-LongM10a #dependence #scheduling: Inversed Temperature Dependence aware clock skew scheduling for sequential circuits (JL, SOM), pp. 1657–1660.
DATE-2010-LongMG #optimisation: Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers (JL, SOM, MG), pp. 117–122.
DAC-2008-LiuMZM #architecture: A power and temperature aware DRAM architecture (SL, SOM, YZ, GM), pp. 878–883.
DAC-2008-LongM #automation #design #pipes and filters #self: Automated design of self-adjusting pipelines (JL, SOM), pp. 211–216.
DAC-2008-NiM #power management #reduction #scheduling: Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction (MN, SOM), pp. 610–613.
DATE-2007-NiM #self: Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DAC-2006-MukherjeeM: Systematic temperature sensor allocation and placement for microprocessors (RM, SOM), pp. 542–547.
DAC-2005-MukherjeeMM #resource management #synthesis: Temperature-aware resource allocation and binding in high-level synthesis (RM, SOM, GM), pp. 196–201.
DAC-2003-MemikMJK #data flow #graph #resource management #synthesis: Global resource sharing for synthesis of control data flow graphs on FPGAs (SOM, GM, RJ, EK), pp. 604–609.