Travelled to:7 × USA
Collaborated with:F.Somenzi D.Grunwald O.Coudert R.W.Haddad R.Bhargava B.Serebrin F.Spadini P.Racunas K.Constantinides S.S.Mukherjee E.Borch E.Tune J.S.Emer M.Arora I.Paul N.Jayasena D.M.Tullsen A.Pardo R.I.Bahar G.D.Hachtel E.Macii M.Poncino
Talks about:system (2) power (2) gate (2) understand (1) dimension (1) benchmark (1) algorithm (1) sequenti (1) behavior (1) virtual (1)
Person: Srilatha Manne
DBLP: Manne:Srilatha
Contributed to:
2015
200820072002
199719961995Wrote 7 papers:
- HPCA-2015-AroraMPJT #behaviour #benchmark #comprehension #cpu #gpu #metric #power management
- Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems (MA, SM, IP, NJ, DMT), pp. 366–377.
- ASPLOS-2008-BhargavaSSM #2d
- Accelerating two-dimensional page walks for virtualized systems (RB, BS, FS, SM), pp. 26–35.
- HPCA-2007-RacunasCMM #fault
- Perturbation-based Fault Screening (PR, KC, SM, SSM), pp. 169–180.
- HPCA-2002-BorchTME
- Loose Loops Sink Chips (EB, ET, SM, JSE), pp. 299–310.
- DAC-1997-ManneGS #locality #memory management
- Remembrance of Things Past: Locality and Memory in BDDs (SM, DG, FS), pp. 196–201.
- DAC-1996-CoudertHM #algorithm #case study #comparative
- New Algorithms for Gate Sizing: A Comparative Study (OC, RWH, SM), pp. 734–739.
- DAC-1995-MannePBHSMP
- Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.