BibSLEIGH — Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe

David Atienza, Giorgio Di Natale
Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2017.

SYS

@proceedings{DATE-2017,
	editor        = "David Atienza and Giorgio Di Natale",
	ee            = "https://ieeexplore.ieee.org/xpl/conhome/7919927/proceeding",
	isbn          = "978-3-9815370-8-6",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2017,
}

Contents (337 items)

DATE-2017-NeugebauerPH: Framework for quantifying and managing accuracy in stochastic circuit design (FN, IP, JPH), pp. 1–6.
DATE-2017-QiqiehSTSY: Energy-efficient approximate multiplier design using bit significance-driven logic compression (IQ, RAS, GT, DS, AY), pp. 7–12.
DATE-2017-LeeAHSC: Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing (VTL, AA, JPH, VS0, LC), pp. 13–18.
DATE-2017-ChenLCDSLJ: Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar (LC, JL, YC, QD, JS, XL, LJ0), pp. 19–24.
DATE-2017-WangCJZZJ: Shared last-level cache management for GPGPUs with hybrid main memory (GW, XC, LJ, CZ, MZ, ZJ), pp. 25–30.
DATE-2017-SadrosadatiMRBS: Effective cache bank placement for GPUs (MS, AM, SR, HB, HSA), pp. 31–36.
DATE-2017-SubramaniyanRSKH: Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores (AS, SR, MS, AK, JH), pp. 37–42.
DATE-2017-PunniyamurthyBG: GATSim: Abstract timing simulation of GPUs (KP, BB, AG), pp. 43–48.
DATE-2017-PoddarJFMDAC: MeSAP: A fast analytic power model for DRAM memories (SP, RJ, LF, GM, GD, AA, HC), pp. 49–54.
DATE-2017-JiLWSP: AFEC: An analytical framework for evaluating cache performance in out-of-order processors (KJ, ML, QW, LS, JP0), pp. 55–60.
DATE-2017-MoriamF: Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approach (SM, GPF), pp. 61–66.
DATE-2017-GhaderiAB: Online monitoring and adaptive routing for aging mitigation in NoCs (ZG, AA0, NB), pp. 67–72.
DATE-2017-SiddharthaK: eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processor (S0, NK), pp. 73–78.
DATE-2017-BarraganLGPR: On the limits of machine learning-based test: A calibrated mixed-signal system case study (MJB, GL, AJG, EJP, AR), pp. 79–84.
DATE-2017-Cliquennois: An extension of Cohn's sensitivity theorem to mismatch analysis of 1-port resistor networks (SC), pp. 85–90.
DATE-2017-LiuLBCHS: Testing microfluidic Fully Programmable Valve Arrays (FPVAs) (CL, BL0, BBB, KC, TYH, US), pp. 91–96.
DATE-2017-ZompakisNNHENPL: HARPA: Tackling physically induced performance variability (NZ, MN, LN, ZH, PE, PN, AP, SL, GM, FS, AB, CN, YS, RV, MG, JS, VV, FC, WF, DS), pp. 97–102.
DATE-2017-CrosKWMABC: Dynamic software randomisation: Lessons learnec from an aerospace case study (FC, LK, FW, DM, JA, IB, FJC), pp. 103–108.
DATE-2017-KjeldsbergGGRSM: READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applications (PGK, AG, MG, LR, JS, USM), pp. 109–114.
DATE-2017-JutmanLLRJRKKE: BASTION: Board and SoC test instrumentation for ageing and no failure found (AJ, CL, EL, MSR, MJ, JR, HGK, RKB, PE), pp. 115–120.
DATE-2017-AliotoCCULA: RETHINK big: European roadmap for hardware anc networking optimizations for big data (GA, PC, AC, OSU, ML, CA), pp. 121–126.
DATE-2017-Alioto: Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computing (MA), pp. 127–132.
DATE-2017-PanN: Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions (CP, AN), pp. 133–138.
DATE-2017-ChengWWLLC: Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective (HPC, WW, CW, SL, HHL, YC), pp. 139–144.
DATE-2017-HorvathHLHN: Cellular neural network friendly convolutional neural networks - CNNs with CNNs (AH, MH, QL, XSH, MTN), pp. 145–150.
DATE-2017-LuoAFW: Algebraic fault analysis of SHA-3 (PL, KA, YF, TW), pp. 151–156.
DATE-2017-KimKHXSS: Evaluating coherence-exploiting hardware Trojan (MK, SK, BH, LX0, WS, TS), pp. 157–162.
DATE-2017-EsirciB: Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations (FNE, AAB), pp. 163–168.
DATE-2017-XuRSM: Malware detection using machine learning based analysis of virtual memory access patterns (ZX, SR, PS, SM), pp. 169–174.
DATE-2017-AmrouchKH: Optimizing temperature guardbands (HA, BK, JH), pp. 175–180.
DATE-2017-BarroisSM: The hidden cost of functional approximation against careful data sizing - A case study (BB, OS, DM), pp. 181–186.
DATE-2017-LeeJG: High-level synthesis of approximate hardware under joint precision and voltage scaling (SL, LKJ, AG), pp. 187–192.
DATE-2017-SenVR: Approximate computing for spiking neural networks (SS, SV, AR), pp. 193–198.
DATE-2017-Ko0NKM: Adaptive weight compression for memory-efficient neural networks (JHK, DK0, TN, JK, SM), pp. 199–204.
DATE-2017-ChenQ: Real-time anomaly detection for streaming data using burst code on a neurosynaptic processor (QC, QQ), pp. 205–207.
DATE-2017-WijesingheL0: Fast, low power evaluation of elementary functions using radial basis function networks (PW, CML, KR0), pp. 208–213.
DATE-2017-BhowmikDB: Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs (BB, JKD, SB), pp. 214–219.
DATE-2017-WangZTT: Recovery-aware proactive TSV repair for electromigration in 3D ICs (SW, HZ, SXDT, MBT), pp. 220–225.
DATE-2017-BundLM: Near-optimal metastability-containing sorting networks (JB, CL, MM), pp. 226–231.
DATE-2017-ZhaoZ: The concept of unschedulability core for optimizing priority assignment in real-time systems (YZ, HZ), pp. 232–237.
DATE-2017-RamanathanE: Utilization difference based partitioned scheduling of mixed-criticality systems (SR, AE), pp. 238–243.
DATE-2017-HatvaniBA: Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with caches (LH, RJB, SA), pp. 244–249.
DATE-2017-LiRLQYDW: Structural design optimization for deep convolutional neural networks using stochastic computing (ZL0, AR, JL0, QQ, BY0, JD, YW), pp. 250–253.
DATE-2017-WangZX: ApproxQA: A unified quality assurance framework for approximate computing (TW0, QZ0, QX0), pp. 254–257.
DATE-2017-MrazekHVS: EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods (VM, RH, ZV, LS), pp. 258–261.
DATE-2017-AluruG: Droop mitigating last level cache architecture for STTRAM (RKA, SG), pp. 262–265.
DATE-2017-MatoussiP: Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation (OM, FP), pp. 266–269.
DATE-2017-FraccaroliF: Analog fault testing through abstraction (EF, FF), pp. 270–273.
DATE-2017-DeyatiMC: BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking (SD, BJM, AC), pp. 274–277.
DATE-2017-AltunCT: Computing with nano-crossbar arrays: Logic synthesis and fault tolerance (MA, VC, MBT), pp. 278–281.
DATE-2017-KelbertGPKPHSFF: SecureCloud: Secure big data processing in untrusted clouds (FK, FG, RP, SK, MP, AH, VS, PF, CF, PRP), pp. 282–285.
DATE-2017-DerrienPABBDDDF: WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach (SD, IP, PA, MB, HB, CD, YD, UD, IF, CF, DH, AK, GKR, SR, MS, TS, KS, TDtB, NSV, JB0), pp. 286–289.
DATE-2017-AndraudBRGXCHVB: Exploring the unknown through successive generations of low power and low resource versatile agents (MA, GB, JDR, SG, HX, EC, PJAH, MV, PGMB), pp. 290–293.
DATE-2017-LodhiHHA: Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit models (FKL, SRH, OH, FRA), pp. 294–297.
DATE-2017-BruestelK: Accounting for systematic errors in approximate computing (MB, AK0), pp. 298–301.
DATE-2017-GhasemazarL: Gaussian mixture error estimation for approximate circuits (AG, ML), pp. 302–305.
DATE-2017-NeubauerWSH: Enhancing symbolic system synthesis through ASPmT with partial assignment evaluation (KN, PW, TS, CH), pp. 306–309.
DATE-2017-BagherzadehB: 3DFAR: A three-dimensional fabric for reliable multi-core processors (JB, VB), pp. 310–313.
DATE-2017-KishaniEA: Evaluating impact of human errors on the availability of data storage systems (MK, RE, HA), pp. 314–317.
DATE-2017-ForsbergMB: GPUguard: Towards supporting a predictable execution model for heterogeneous SoC (BF, AM, LB), pp. 318–321.
DATE-2017-Li0MWH: A non-intrusive, operating system independent spinlock profiler for embedded multicore systems (LL, PW0, AM, TW, AH), pp. 322–325.
DATE-2017-BahadoriRPGTWPB: Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing (MB, SR, RPP, AG, MT, MW, KP, KB), pp. 326–331.
DATE-2017-Patel: Rapid growth of IP traffic is driving adoption of silicon photonics in data centers (KP), pp. 332–335.
DATE-2017-ReimerKRWLCCMM: Generation of complex quantum states via integrated frequency combs (CR, MK, PR, BW, BEL, STC, LC, DJM, RM), pp. 336–337.
DATE-2017-RaitzaKVWTMW: Exploiting transistor-level reconfiguration to optimize combinational circuits (MR, AK0, MV, DW, JT, TM, WMW), pp. 338–343.
DATE-2017-KrishnaBCZWWLMP: Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process (TK, AB, SBC, LZ, BW, CW, KEKL, JM, LSP), pp. 344–349.
DATE-2017-HeF: A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network (ZH, DF), pp. 350–355.
DATE-2017-RanjanVPV0R: STAxCache: An approximate, energy efficient STT-MRAM cache (AR, SV, ZP, RV, KR0, AR), pp. 356–361.
DATE-2017-HameedC: Rethinking on-chip DRAM cache for simultaneous performance and energy optimization (FH, JC), pp. 362–367.
DATE-2017-JostNC: An energy-efficient memory hierarchy for multi-issue processors (TTJ, GLN, LC), pp. 368–373.
DATE-2017-FengFYTL: Mapping granularity adaptive FTL based on flash page re-programming (YF, DF0, CY, WT, JL), pp. 374–379.
DATE-2017-HassanHLCGD: Data flow testing for virtual prototypes (MH, VH, HML, MC, DG, RD), pp. 380–385.
DATE-2017-SenDK: MINIME-validator: Validating hardware with synthetic parallel testcases (AS, ED, BK), pp. 386–391.
DATE-2017-FarahmandiMZNM: Cost-effective analysis of post-silicon functional coverage events (FF, RM, AZ, ZN, PM0), pp. 392–397.
DATE-2017-OBrienTDB: Towards exascale computing with heterogeneous architectures (KO, LDT, GD, MB), pp. 398–403.
DATE-2017-BeckerBNPRG: From exaflop to exaflow (TB, PB, AMN, HP, ER, GG), pp. 404–409.
DATE-2017-RabozziNSSSS: Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project (MR, GN, EDS, AS, LS, MDS), pp. 410–415.
DATE-2017-StroobandtCSFBP: An open reconfigurable research platform as stepping stone to exascale high-performance computing (DS, CBC, MDS, GF, AB, DNP, MH, TB, AJWT), pp. 416–421.
DATE-2017-BurchardESR0: Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG (JB, DE, ADS, SMR, BB0), pp. 422–427.
DATE-2017-YeQH0: Fault diagnosis of arbiter physical unclonable function (JY, QQ, YH, XL0), pp. 428–433.
DATE-2017-ZhangWHXZX: FPGA-based failure mode testing and analysis for MLC NAND flash memory (MZ0, FW0, HH, QX, JZ0, CX), pp. 434–439.
DATE-2017-BanaGozarMKAP: Robust neuromorphic computing in the presence of process variation (AB, MAM, MK, AAK, MP), pp. 440–445.
DATE-2017-MaCDWH: An on-line framework for improving reliability of real-time systems on “big-little” type MPSoCs (YM0, TC, RPD, SW, XSH), pp. 446–451.
DATE-2017-MaragosLSSP: Application performance improvement by exploiting process variability on FPGA devices (KM, GL, DS, KS, VFP), pp. 452–457.
DATE-2017-ZulehnerW: Make it reversible: Efficient embedding of non-reversible functions (AZ, RW), pp. 458–463.
DATE-2017-KhammassiAFAB: QX: A high-performance quantum computer simulation platform (NK, IA, XF, CGA, KB), pp. 464–469.
DATE-2017-SoekenRWM: Design automation and design space exploration for quantum computers (MS, MR, NW, GDM), pp. 470–475.
DATE-2017-RagavanBKS: Pushing the limits of voltage over-scaling for error-resilient applications (RR, BB, CK, OS), pp. 476–481.
DATE-2017-JiaoCCJEG: Combining structural and timing errors in overclocked inexact speculative adders (XJ, VC, MC, YJ0, CE, RKG0), pp. 482–487.
DATE-2017-MoonsUDV: DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling (BM, RU, WD, MV), pp. 488–493.
DATE-2017-MercatBPHM: Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case study (AM, JB, MP, WH, DM), pp. 494–499.
DATE-2017-GonzalezLSPMNPH: Location detection for navigation using IMUs with a map through coarse-grained machine learning (EJJG, CL, AS, KVP, YM, SN, DP, SH), pp. 500–505.
DATE-2017-DoyleMHFS: Performance impacts and limitations of hardware memory access trace collection (NCD, EM, GMH, AF, LS), pp. 506–511.
DATE-2017-OttlikGVRB: Context-sensitive timing automata for fast source level simulation (SO, CG, AV, WR, OB0), pp. 512–517.
DATE-2017-EidenbenzMSF: MARS: A flexible real-time streaming platform for testing automation systems (RE, AM, TS, CF), pp. 518–523.
DATE-2017-GhoshD: SERD: A simulation framework for estimation of system level reliability degradation (SKG, SD), pp. 524–529.
DATE-2017-SrinivasanS0: Magnetic tunnel junction enabled all-spin stochastic spiking neural network (GS, AS, KR0), pp. 530–535.
DATE-2017-SenniDCPTGBS: Embedded systems to high performance computing using STT-MRAM (SS, TD, OC, PYP, LT, AG, PB, GS), pp. 536–541.
DATE-2017-KangCZZ: Voltage-controlled MRAM for working memory: Perspectives and challenges (WK, LC0, YZ, WZ), pp. 542–547.
DATE-2017-HanyuSON: Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor (TH, DS, NO, MN), pp. 548–553.
DATE-2017-SayedEBT: Opportunistic write for fast and reliable STT-MRAM (NS, ME, RB, MBT), pp. 554–559.
DATE-2017-LiHLLJ: Fault clustering technique for 3D memory BISR (TL, YH, XL, HHSL, LJ0), pp. 560–565.
DATE-2017-ChenCBH: Architectural evaluations on TSV redundancy for reliability enhancement (YHC, CPC, RB, TH), pp. 566–571.
DATE-2017-JindalPS: Reusing trace buffers to enhance cache performance (NJ, PRP, SRS), pp. 572–577.
DATE-2017-HuhnECD: Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression (SH0, SE, KC, RD), pp. 578–583.
DATE-2017-HammadehEQHR: Bounding deadline misses in weakly-hard real-time systems with task dependencies (ZAHH, RE, SQ, RH, LR), pp. 584–589.
DATE-2017-TobuschatE: Real-time communication analysis for Networks-on-Chip with backpressure (ST, RE), pp. 590–595.
DATE-2017-AbdeddaimM: Probabilistic schedulability analysis for fixed priority mixed criticality real-time systems (YA, DM), pp. 596–601.
DATE-2017-WuWZZSBC: Compact modeling and circuit-level simulation of silicon nanophotonic interconnects (RW, YW, ZZ, CZ, CLS, JEB0, KTC), pp. 602–605.
DATE-2017-QuHCPZZ: A true random number generator based on parallel STT-MTJs (YQ, JH0, BFC, WP, YZ0, WZ), pp. 606–609.
DATE-2017-ChaouraniHDOR: Enabling area efficient RF ICs through monolithic 3D integration (PC, PEH, SRD, RO, AR), pp. 610–613.
DATE-2017-KuttappaKNT: Reconfigurable threshold logic gates using optoelectronic capacitors (RK, LK, BN, BT), pp. 614–617.
DATE-2017-XuHYYW: i-BEP: A non-redundant and high-concurrency memory persistency model (YX, ZH, JY, LY, HW0), pp. 618–621.
DATE-2017-LiWXSL: SPMS: Strand based persistent memory system (SL0, PW0, NX, GS0, FL0), pp. 622–625.
DATE-2017-EccoE: Architecting high-speed command schedulers for open-row real-time SDRAM controllers (LE, RE), pp. 626–629.
DATE-2017-GoliSD: Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications (MG, JS, RD), pp. 630–633.
DATE-2017-MaG: Head-mounted sensors and wearable computing for automatic tunnel vision assessment (YM, HG), pp. 634–637.
DATE-2017-WangLXZWG: RetroDMR: Troubleshooting non-deterministic faults with retrospective DMR (TW0, YL, QX0, ZZ, ZW, XG), pp. 638–641.
DATE-2017-VartziotisK: Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage (FV, XK), pp. 642–645.
DATE-2017-AppelloBGMPPRRR: A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC (DA, PB, GG, AM, AP, GP, CR, MR, PR, ES0, CMV, FV), pp. 646–649.
DATE-2017-LiuH: Energy efficient stochastic computing with Sobol sequences (SL, JH0), pp. 650–653.
DATE-2017-BaigM: Logic analysis and verification of n-input genetic logic circuits (HB, JM), pp. 654–657.
DATE-2017-NikolaosGP: A novel way to efficiently simulate complex full systems incorporating hardware accelerators (NT, KG, YP), pp. 658–661.
DATE-2017-FraccaroliLF: Automatic abstraction of multi-discipline analog models for efficient functional simulation (EF, ML, FF), pp. 662–665.
DATE-2017-KhanIG: Novel magnetic burn-in for retention testing of STTRAM (MNIK, ASI, SG), pp. 666–669.
DATE-2017-NiakiS: Automatic construction of models for analytic system-level design space exploration problems (SHAN, IS), pp. 670–673.
DATE-2017-Schaumont: Security in the Internet of Things: A challenge of scale (PS), pp. 674–679.
DATE-2017-SauerRF0RP: Sensitized path PUF: A lightweight embedded physical unclonable function (MS0, PR, LF, BB0, UR, IP), pp. 680–685.
DATE-2017-TaoD: Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators (ST, ED), pp. 686–691.
DATE-2017-SantisSS: ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications (FDS, AS, GS), pp. 692–697.
DATE-2017-GuillenPMBSS: Towards post-quantum security for IoT endpoints with NTRU (OMG, TP, JMBM, EFB, GS, JS), pp. 698–703.
DATE-2017-IstoanD: Automating the pipeline of arithmetic datapaths (MI, FdD), pp. 704–709.
DATE-2017-SantosOTAAC: Operand size reconfiguration for big data processing in memory (PCS, GFO, DGT, MAZA, ECdA, LC), pp. 710–715.
DATE-2017-TucciOBS: Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL (LDT, KO, MB, MDS), pp. 716–721.
DATE-2017-HamdiouiKCXWJEC: Memristor for computing: Myth or reality? (SH, SK, GC, LX0, NW, SJ, HME, HC, KB), pp. 722–731.
DATE-2017-JiangBMNBS: An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart (WJ, DB, GM, SMN, WPB, GS), pp. 732–733.
DATE-2017-TekleyohannesSW: An advanced embedded architecture for connected component analysis in industrial applications (MT, MS, CW, NW, MK0, MS), pp. 734–735.
DATE-2017-SivadasanNHMMCA: Workload dependent reliability timing analysis flow (AS, AN, VH, EM, SM, FC, LA), pp. 736–737.
DATE-2017-FernandezMKBBHQ: Probabilistic timing analysis on time-randomized platforms for the space domain (MF, DM, LK, AB, IB, CH, EQ, JA, FJC, PM, LF), pp. 738–739.
DATE-2017-MasinPMFPPRRSTT: Cross-layer design of reconfigurable cyber-physical systems (MM, FP, HM, JAdOF, MP, MP, LR, FR0, AAS, AT, EdlT, KZ), pp. 740–745.
DATE-2017-LesecqFBCJCHBMP: INSPEX: Design and integration of a portable/wearable smart spatial exploration system (SL, JF, FB, HdC, CJ, MC, PH, RB, ADM, VDP, JB, SR, JMVG, CO, AM), pp. 746–751.
DATE-2017-SkalistisS: Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees (SS, AS), pp. 752–757.
DATE-2017-Naderlinger: Simulating preemptive scheduling with timing-aware blocks in Simulink (AN), pp. 758–763.
DATE-2017-HuHCCK: Online workload monitoring with the feedback of actual execution time for real-time systems (BH, KH0, GC0, LC0, AK), pp. 764–769.
DATE-2017-ChakrabortyJ: Automated synthesis of compact crossbars for sneak-path based in-memory computing (DC, SKJ0), pp. 770–775.
DATE-2017-HassanYLLC: Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays (AMH, CY, CL, HHL, YC), pp. 776–781.
DATE-2017-BhattacharjeeDC: ReVAMP: ReRAM based VLIW architecture for in-memory computing (DB, RD, AC), pp. 782–787.
DATE-2017-HoAKP: Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor (NH, IIA, PK, MP), pp. 788–793.
DATE-2017-BhadraS: Design of a low power, relative timing based asynchronous MSP430 microprocessor (DB, KSS), pp. 794–799.
DATE-2017-JainPS: A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning (RJ, PRP, SS), pp. 800–805.
DATE-2017-JiangA: GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems (ZJ0, NCA), pp. 806–811.
DATE-2017-SasaoMI: An algorithm to find optimum support-reducing decompositions for index generation functions (TS, KM, YI), pp. 812–817.
DATE-2017-ZulehnerW17a: Taking one-to-one mappings for granted: Advanced logic design of encoder circuits (AZ, RW), pp. 818–823.
DATE-2017-AfonsoM: Analysis of short-circuit conditions in logic circuits (JA, JCM), pp. 824–829.
DATE-2017-SoekenMM: Busy man's synthesis: Combinational delay optimization with SAT (MS, GDM, AM), pp. 830–835.
DATE-2017-AlmudeverLFKAIV: The engineering challenges in quantum computing (CGA, LL, XF, NK, IA, DI, SV, CE, AW, LG, AK, JK, HB, KB), pp. 836–845.
DATE-2017-LeeY: MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliability (SYL, JSY), pp. 846–851.
DATE-2017-KinseherHP: Analyzing the effects of peripheral circuit aging of embedded SRAM architectures (JK, LH, IP), pp. 852–857.
DATE-2017-KraakATHWCCD: Mitigation of sense amplifier degradation using input switching (DK, IA, MT, SH, PW, SC, FC, WD), pp. 858–863.
DATE-2017-PathaniaKSMH: Scalable probabilistic power budgeting for many-cores (AP, HK, MS0, TM, JH), pp. 864–869.
DATE-2017-BeckertGE: Exploiting sporadic servers to provide budget scheduling for ARINC653 based real-time virtualization environments (MB, KBG, RE), pp. 870–875.
DATE-2017-KampenhoutSG: Programming and analysing scenario-aware dataflow on a multi-processor platform (RvK, SS, KG), pp. 876–881.
DATE-2017-KiamehrGT: Leveraging aging effect to improve SRAM-based true random number generators (SK, MSG, MBT), pp. 882–885.
DATE-2017-KeshavarzPH: Design automation for obfuscated circuits with multiple viable functions (SK, CP, DEH), pp. 886–889.
DATE-2017-NguyenKL: Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs (DN0, DK, JL), pp. 890–893.
DATE-2017-PhamHK: BITMAN: A tool and API for FPGA bitstream manipulations (KDP, ELH, DK), pp. 894–897.
DATE-2017-GerlachSRE: A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example (AG, JS, TR, FTE), pp. 898–901.
DATE-2017-KuiperB: Latency analysis of homogeneous synchronous dataflow graphs using timed automata (GK, MJGB), pp. 902–905.
DATE-2017-SwamiM: COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories (SS, KM), pp. 906–909.
DATE-2017-HuangFHZ: A wear-leveling-aware counter mode for data encryption in non-volatile memories (FH, DF0, YH0, WZ), pp. 910–913.
DATE-2017-GuptaMVAA: Tunnel FET based refresh-free-DRAM (NG, AM, AV, AA, CA), pp. 914–917.
DATE-2017-PatelKMS: A hardware implementation of the MCAS synchronization primitive (SP, RK, IM, SRS), pp. 918–921.
DATE-2017-ZhangG: BandiTS: Dynamic timing speculation using multi-armed bandit based optimization (JJZ, SG), pp. 922–925.
DATE-2017-SlijepcevicHAC: Design and implementation of a fair credit-based bandwidth sharing scheme for buses (MS, CH, JA, FJC), pp. 926–929.
DATE-2017-ZhangD: Technology mapping with all spin logic (BZ0, AD), pp. 930–933.
DATE-2017-MozaffariTH: A new method to identify threshold logic functions (SNM, ST, TH), pp. 934–937.
DATE-2017-Pomeranz: A bridging fault model for line coverage in the presence of undetected transition faults (IP), pp. 938–941.
DATE-2017-HanPB: CHRT: A criticality- and heterogeneity-aware runtime system for task-parallel applications (MH, JP, WB), pp. 942–945.
DATE-2017-DongYGKJ: MobiXen: Porting Xen on Android devices for mobile virtualization (YD, JY, HG, RAK, YJ), pp. 946–949.
DATE-2017-TrompoukiK: Optimisation opportunities and evaluation for GPGPU applications on low-end mobile GPUs (MMT, LK), pp. 950–953.
DATE-2017-HenkelPABS: Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies) (JH, SP, HA, LB, FS), pp. 954–959.
DATE-2017-MerrettA: Energy-driven computing: Rethinking the design of energy harvesting systems (GVM, BMAH), pp. 960–965.
DATE-2017-SuMLWLN: Nonvolatile processors: Why is it trending? (FS, KM, XL, TW, YL, VN), pp. 966–971.
DATE-2017-PerriconeALMHKN: Advanced spintronic memory and logic for non-volatile processors (RP, IA0, ZL, MGM, XSH, CHK, MTN, SSS, JW0), pp. 972–977.
DATE-2017-UenoHMA: Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme (RU, NH, SM, TA), pp. 978–983.
DATE-2017-BianHS: SCAM: Secured content addressable memory based on homomorphic encryption (SB, MH, TS), pp. 984–989.
DATE-2017-BacheS0G: SPARX - A side-channel protected processor for ARX-based cryptography (FB, TS0, AM0, TG), pp. 990–995.
DATE-2017-FallahzadehOG: Adaptive compressed sensing at the fingertip of Internet-of-Things sensors: An ultra-low power activity recognition (RF, JPO, HG), pp. 996–1001.
DATE-2017-BoschmannTWWP: A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller (AB, GT, LW, AW, MP), pp. 1002–1007.
DATE-2017-JiangBKKS: Microwatt end-to-End digital neural signal processing systems for motor intention decoding (ZJ, CB, JK, SJK, MS), pp. 1008–1013.
DATE-2017-VenutoAM: An embedded system remotely driving mechanical devices by P300 brain activity (DDV, VFA, GM), pp. 1014–1019.
DATE-2017-BalSRC: Revamping timing error resilience to tackle choke points at NTC systems (AB, SS, SR, KC), pp. 1020–1025.
DATE-2017-ImaniPKRR: Efficient neural network acceleration on GPGPU using content addressable memory (MI, DP, YK, AR, TR), pp. 1026–1031.
DATE-2017-WangZHY: Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks (SW, DZ, XH, TY), pp. 1032–1037.
DATE-2017-BeneventiBCB: Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools (FB, AB, CC, LB), pp. 1038–1043.
DATE-2017-Lewis: Self-aware computing systems: From psychology to engineering (PRL), pp. 1044–1049.
DATE-2017-SchlatowMENJMHH: Self-awareness in autonomous automotive systems (JS, MM, RE, MN, IJ, MM, CH, AH), pp. 1050–1055.
DATE-2017-AnzanpourAGRTLJ: Self-awareness in remote health monitoring systems using wearable electronics (AA, IA, MG, AMR, NT, PL, AJ, NDD), pp. 1056–1061.
DATE-2017-RokickiRD: Hardware-accelerated dynamic binary translation (SR, ER, SD), pp. 1062–1067.
DATE-2017-MoussawiD: Superword level parallelism aware word length optimization (AHEM, SD), pp. 1068–1073.
DATE-2017-LuppoldF: Schedulability-aware SPM Allocation for preemptive hard real-time systems with arbitrary activation patterns (AL, HF), pp. 1074–1079.
DATE-2017-LiFHWJZ: A Log-aware Synergized scheme for page-level FTL design (CL, DF0, YH0, FW0, CJ, WZ0), pp. 1080–1085.
DATE-2017-ChenJLLGL: MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systems (DC, HJ0, XL, HL, RG, DL), pp. 1086–1091.
DATE-2017-ShirinzadehSGMD: Endurance management for resistive Logic-In-Memory computing architectures (SS, MS, PEG, GDM, RD), pp. 1092–1097.
DATE-2017-TavanaZK: Live together or Die Alone: Block cooperation to extend lifetime of resistive memories (MKT, AKZ, DRK), pp. 1098–1103.
DATE-2017-ChattopadhyayPS: Secure Cyber-Physical Systems: Current trends, tools and open research problems (AC, AP, MS0), pp. 1104–1109.
DATE-2017-JungkB: Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305 (BJ, SB), pp. 1110–1115.
DATE-2017-Mutlu: The RowHammer problem and other issues we may face as memory becomes denser (OM), pp. 1116–1121.
DATE-2017-JacobRZHS: Compromising FPGA SoCs using malicious hardware blocks (NJ, CR, AZ, JH, GS), pp. 1122–1127.
DATE-2017-Garg: Inspiring trust in outsourced integrated circuit fabrication (SG), p. 1128.
DATE-2017-DangerGNNS: Analyzing security breaches of countermeasures throughout the refinement process in hardware design flow (JLD, SG, PN, RN, YS), pp. 1129–1134.
DATE-2017-PourmohseniGT: Automatic operating point distillation for hybrid mapping methodologies (BP, MG, JT), pp. 1135–1140.
DATE-2017-ZhongPWLMN: Design Space exploration of FPGA-based accelerators with multi-level parallelism (GZ, AP, SW, YL0, TM, SN), pp. 1141–1146.
DATE-2017-RahmanOLC: Design space exploration of FPGA accelerators for convolutional neural networks (AR, SO, JL, KC), pp. 1147–1152.
DATE-2017-BarrioH: A slack-based approach to efficiently deploy radix 8 booth multipliers (AADB, RH), pp. 1153–1158.
DATE-2017-SigristGLLLT: Measurement and validation of energy harvesting IoT devices (LS, AG0, RL, SL, ML, LT), pp. 1159–1164.
DATE-2017-PagliariDCMBMP: A methodology for the design of dynamic accuracy operators by runtime back bias (DJP, YD, DC, AM, EB, EM, MP), pp. 1165–1170.
DATE-2017-HagerFGB: A scan-chain based state retention methodology for IoT processors operating on intermittent energy (PAH, HF, JPdG, LB), pp. 1171–1176.
DATE-2017-ChenMP: A circuit-equivalent battery model accounting for the dependency on load frequency (YC, EM, MP), pp. 1177–1182.
DATE-2017-JiaoJRG: SLoT: A supervised learning model to predict dynamic timing errors of functional units (XJ, YJ0, AR, RKG0), pp. 1183–1188.
DATE-2017-ChandraL: Exploiting data-dependence and Flip-Flop asymmetry for zero-overhead system soft error mitigation (VC, LL), pp. 1189–1194.
DATE-2017-LvYYZZ: Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits (WL, FY0, CY, DZ, XZ0), pp. 1195–1200.
DATE-2017-CanelasMP0H: Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing (AC, RM0, RP, NL0, NH), pp. 1201–1206.
DATE-2017-YanZZZ: An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid (CY, HZ, DZ, XZ0), pp. 1207–1212.
DATE-2017-ShahsavaniSNP: A thermally-aware energy minimization methodology for global interconnects (SNS, AS, SN, MP), pp. 1213–1218.
DATE-2017-TsaiCHW: Analysis and optimization of variable-latency designs in the presence of timing variability (CLT, CWC, NCH, KCW), pp. 1219–1224.
DATE-2017-AngioliniISYATM: 1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA (FA, AI, WAS, ACY, MA, JPT, GDM), pp. 1225–1228.
DATE-2017-LorenzonSB: LAANT: A library to automatically optimize EDP for OpenMP applications (AFL, JDS, ACSB), pp. 1229–1232.
DATE-2017-ChinTHH: Improving the accuracy of the leakage power estimation of embedded CPUs (TWC, SLT, KWH, PSH), pp. 1233–1236.
DATE-2017-AguilarLAKF: Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack (MAA, RL, GA, NK, LF), pp. 1237–1240.
DATE-2017-CaiKKSL: Reducing code management overhead in software-managed multicores (JC0, YK, YK, AS, KL), pp. 1241–1244.
DATE-2017-ZhuZWCX: Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications (MZ, YZ, CW, WC, YX0), pp. 1245–1248.
DATE-2017-ParkLK: DAC: Dedup-assisted compression scheme for improving lifetime of NAND storage systems (JP, SL, JK), pp. 1249–1252.
DATE-2017-WangWLZXZX: Lifetime adaptive ECC in NAND flash page management (SW, FW0, ZL, YZ, QX, MZ0, CX), pp. 1253–1556.
DATE-2017-Lastras-Montano: 3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing (MALM, BC, DBS, KTC), pp. 1257–1260.
DATE-2017-KimBAS: A schedulability test for software migration on multicore system (JEK, RMB, TFA, LS), pp. 1261–1264.
DATE-2017-LiXWYMT: Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators (HL, JX0, ZW0, PY0, RKVM, ZT), pp. 1265–1268.
DATE-2017-MiMS: Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators (XM, HFM, JsS), pp. 1269–1272.
DATE-2017-LahiouelZT: Enhancing analog yield optimization for variation-aware circuits sizing (OL, MHZ, ST), pp. 1273–1276.
DATE-2017-MahmoudiZ: A new sampling technique for Monte Carlo-based statistical circuit analysis (HM, HZ), pp. 1277–1280.
DATE-2017-CachacoMLGH: Automatic technology migration of analog IC designs using generic cell libraries (JC, NM, NL0, JG, NH), pp. 1281–1284.
DATE-2017-LiLHS: Noise-sensitive feedback loop identification in linear time-varying analog circuits (AL, PL0, TH, ESS), pp. 1285–1288.
DATE-2017-BukhariLHSH: CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking (SAAB, FKL, OH, MS0, JH), pp. 1289–1292.
DATE-2017-AbdelkaderED: Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits (SA, AE, MD), pp. 1293–1296.
DATE-2017-PaganFGMRA: An optimal approach for low-power migraine prediction models in the state-of-the-art wireless monitoring devices (JP, RF, HG, JMM, JLRM, JLA), pp. 1297–1302.
DATE-2017-AmaruVLO: Logic optimization and synthesis: Trends and directions in industry (LGA, PV, JL, JO), pp. 1303–1305.
DATE-2017-ZografosMTSGMAR: Wave pipelining for majority-based beyond-CMOS technologies (OZ, ADM, ET, MS, PEG, GDM, LGA, PR, FC, RL), pp. 1306–1311.
DATE-2017-RottelerSWW: Design automation for quantum architectures (MR, KMS, DW, NW), pp. 1312–1317.
DATE-2017-UnterluggauerWM: Side-channel plaintext-recovery attacks on leakage-resilient encryption (TU, MW, SM), pp. 1318–1323.
DATE-2017-Moos0R: Static power side-channel analysis of a threshold implementation prototype chip (TM, AM0, BR), pp. 1324–1329.
DATE-2017-LuoFD: Side-channel power analysis of XTS-AES (CL, YF, AAD), pp. 1330–1335.
DATE-2017-TianRWSMS: A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration (JT, GRR, JW, WS, YM, CS), pp. 1336–1341.
DATE-2017-SeifooriKA: A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era (ZS, BK, HA), pp. 1342–1347.
DATE-2017-ZhaoSHML: A static-placement, dynamic-issue framework for CGRA loop accelerator (ZZ, WS, WH, ZM, ZL), pp. 1348–1353.
DATE-2017-DiTomasoSKL: Machine learning enabled power-aware Network-on-Chip design (DD, MAIS, AKK, AL), pp. 1354–1359.
DATE-2017-DuraisamyP: Performance evaluation and design trade-offs for wireless-enabled SMART NoC (KD, PPP), pp. 1360–1365.
DATE-2017-DasDPC: Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noise (SD, JRD, PPP, KC), pp. 1366–1371.
DATE-2017-LuoEPKCBSO: Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoC (JL, AE, VDP, CK, DC, SLB, OS, IO), pp. 1372–1377.
DATE-2017-NizAKKPR: Mixed-criticality processing pipelines (DdN, BA, HK, MHK, LTXP, RR), pp. 1372–1375.
DATE-2017-RustP: Exploiting special-purpose function approximation for hardware-efficient QR-decomposition (JR, SP), pp. 1378–1383.
DATE-2017-El-HarouniRP0HS: Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding (WEH, SR, BSP, AK0, RH, MS0), pp. 1384–1389.
DATE-2017-RybalkinWYS: Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition (VR, NW, MRY, DS), pp. 1390–1395.
DATE-2017-MaoCNKC: MoDNN: Local distributed mobile computing system for Deep Neural Network (JM, XC0, KWN, CDK, YC), pp. 1396–1401.
DATE-2017-ZhouYWCH: Energy-adaptive scheduling of imprecise computation tasks for QoS optimization in real-Time MPSoC systems (JZ, JY, TW, MC, XSH), pp. 1402–1407.
DATE-2017-ChhetriFF: Fix the leak! an information leakage aware secured cyber-physical manufacturing system (SRC, SF, MAAF), pp. 1408–1413.
DATE-2017-FengGLLDL0: Efficient drone hijacking detection using onboard motion sensors (ZF, NG, ML, WL, QD, XL0, WY0), pp. 1414–1419.
DATE-2017-CerinaS: Reconfigurable embedded systems applications for versatile biomedical measurements (LC, MDS), pp. 1420–1425.
DATE-2017-RuediBAPNPEC: Ultra low power microelectronics for wearable and medical devices (PFR, AB, MKA, PP, JLN, MP, SE, OC), pp. 1426–1431.
DATE-2017-MilosevicBF: Design challenges for wearable EMG applications (BM, SB, EF), pp. 1432–1437.
DATE-2017-WangPLPGAWG: Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing (SW, SP, TL, AP, CG, PKA, KLW, PG), pp. 1438–1443.
DATE-2017-YinNH: Design and benchmarking of ferroelectric FET based TCAM (XY, MTN, XSH), pp. 1444–1449.
DATE-2017-KhouzaniFYG: Leveraging access port positions to accelerate page table walk in DWM-based main memory (HAK, PF, CY, GRG), pp. 1450–1455.
DATE-2017-NairBGOT: VAET-STT: A variation aware estimator tool for STT-MRAM based memories (SMN, RB, MSG, FO, MBT), pp. 1456–1461.
DATE-2017-KimAY: A novel zero weight/activation-aware hardware architecture of convolutional neural network (DK, JA, SY), pp. 1462–1467.
DATE-2017-BrandaleroB: A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams (MB, ACSB), pp. 1468–1473.
DATE-2017-HashemiATBR: Understanding the impact of precision quantization on the accuracy and energy of neural networks (SH, NA, HT, RIB, SR), pp. 1474–1479.
DATE-2017-MalikNMSH: Big vs little core for energy-efficient Hadoop computing (MM, KN, TM, AS, HH), pp. 1480–1485.
DATE-2017-MurraySBC: Quantifying error: Extending static timing analysis with probabilistic transitions (KEM, AS, VB, GAC), pp. 1486–1491.
DATE-2017-ChenWW: On refining standard cell placement for self-aligned double patterning (YHC, SHW, TCW), pp. 1492–1497.
DATE-2017-PonghiranSS: Cut mask optimization for multi-patterning directed self-assembly lithography (WP, SS, YS), pp. 1498–1503.
DATE-2017-NaKM: Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation (TN, JHK, SM), pp. 1504–1509.
DATE-2017-HoettgerIS: On reducing busy waiting in autosar via task-release-delta-based runnable reordering (RH, BI, OS), pp. 1510–1515.
DATE-2017-FletcherBM: Power neutral performance scaling for energy harvesting MP-SoCs (BJF, DB, GVM), pp. 1516–1521.
DATE-2017-ShivaramanES: Efficient decentralized active balancing strategy for smart battery cells (NS, AE, SS), pp. 1522–1527.
DATE-2017-MagnoAGBB: WULoRa: An energy efficient IoT end-node for energy harvesting and heterogeneous communication (MM, FAA, MG, OB, LB), pp. 1528–1533.
DATE-2017-MaW: Characterization of stack behavior under soft errors (JM, YW), pp. 1534–1539.
DATE-2017-MaMM: Multi-armed bandits for efficient lifetime estimation in MPSoC design (CM, AM, BHM), pp. 1540–1545.
DATE-2017-ZhouM: Hardware-based on-line intrusion detection via system call routine fingerprinting (LZ, YM), pp. 1546–1551.
DATE-2017-JaschkeHWSZ: Static netlist verification for IBM high-frequency processors using a tree-grammar (CJ, UH, CW, CS, CGZ), pp. 1552–1557.
DATE-2017-YuHC: Reverse engineering of irreducible polynomials in GF(2m) arithmetic (CY, DEH, MJC), pp. 1558–1563.
DATE-2017-SiddiqueHJ: Formal specification and dependability analysis of optical communication networks (US, KAH, TTJ), pp. 1564–1569.
DATE-2017-BaleCTWT: An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architecture (SJB, PBC, MAT, JAW, AMT), pp. 1570–1575.
DATE-2017-VasicekMS: Towards low power approximate DCT architecture for HEVC standard (ZV, VM, LS), pp. 1576–1581.
DATE-2017-Panda0: Semantic driven hierarchical learning for energy-efficient image classification (PP, KR0), pp. 1582–1587.
DATE-2017-BiswasBSAM: Machine learning for run-time energy optimisation in many-core systems (DB, VB, RAS, BMAH, GVM), pp. 1588–1592.
DATE-2017-MarcelliRSS: An evolutionary approach to hardware encryption and Trojan-horse mitigation (AM, MR, ES0, GS), pp. 1593–1598.
DATE-2017-SimonovicZS: Formal model for system-level power management design (MS, VZ, LS), pp. 1599–1602.
DATE-2017-GuanZS: Extending memory capacity of neural associative memory based on recursive synaptic bit reuse (TG, XZ, MS), pp. 1603–1606.
DATE-2017-AminifarB: Anomalies in scheduling control applications and design complexity (AA, EB), pp. 1607–1610.
DATE-2017-SehnkeSE: Contract-based integration of automotive control software (TS, MS, RE), pp. 1611–1614.
DATE-2017-FuGRJS: Modeling and integrating physical environment assumptions in medical cyber-physical system design (ZF, CG, SR, YJ0, LS), pp. 1615–1618.
DATE-2017-ChattopadhyayBY: A utility-driven data transmission optimization strategy in large scale cyber-physical systems (SC, AB, BY0), pp. 1619–1622.
DATE-2017-MaoZSS: Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss (HM, XZ, GS, JS), pp. 1623–1626.
DATE-2017-SchneiderKSD: Effects of cell shapes on the routability of Digital Microfluidic Biochips (LS, OK, JS, RD), pp. 1627–1630.
DATE-2017-KulkarniSHM: LESS: Big data sketching and Encryption on low power platform (AMK, CS, HH, TM), pp. 1631–1634.
DATE-2017-VahdatKAPN: TruncApp: A truncation-based approximate divider for energy efficient DSP applications (SV, MK, AAK, MP, ZN), pp. 1635–1638.
DATE-2017-SongKS: Timing-aware wire width optimization for SADP process (YS, SK, YS), pp. 1639–1642.
DATE-2017-SmirnovGRT: Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks (FS, MG, FR, JT), pp. 1643–1646.
DATE-2017-PalossiMB: Ultra low-power visual odometry for nano-scale unmanned aerial vehicles (DP, AM, LB), pp. 1647–1650.
DATE-2017-RossiTGTCCB: Long range wireless sensing powered by plant-microbial fuel cell (MR, PT, LG, LT, CC, SC, DB), pp. 1651–1654.
DATE-2017-LombardPAM: On the cooperative automatic lane change: Speed synchronization and automatic “courtesy” (AL, FP, AAT, AEM), pp. 1655–1658.
DATE-2017-GolnariM: Evaluating matrix representations for error-tolerant computing (PAG, SM), pp. 1659–1662.
DATE-2017-OsipovP: Simulation-based design procedure for sub 1V CMOS current reference (DO0, SP), pp. 1663–1666.
DATE-2017-HuangG0HP: Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochips (WLH, AG0, SR0, TYH, PP), pp. 1667–1672.
DATE-2017-IbrahimCS: CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform (MI0, KC, US), pp. 1673–1678.
DATE-2017-GrimmerHSW: Verification of networked Labs-on-Chip architectures (AG, WH, AS, RW), pp. 1679–1684.
DATE-2017-KimC: Synthesis of activation-parallel convolution structures for neuromorphic architectures (SK, JC), pp. 1685–1690.
DATE-2017-ArdeshirichamHM: Register transfer level information flow tracking for provably secure hardware design (AA, WH0, JM, RK), pp. 1691–1696.
DATE-2017-ReparazBV: Dude, is my code constant time? (OR, JB, IV), pp. 1697–1702.
DATE-2017-BidmeshkiAM: Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP (MMB, AA0, YM), pp. 1703–1708.
DATE-2017-ZhengVSJG: Sampling-based binary-level cross-platform performance estimation (XZ, HV, SS, LKJ, AG), pp. 1709–1714.
DATE-2017-UngureanuS: A layered formal framework for modeling of cyber-physical systems (GU, IS), pp. 1715–1720.
DATE-2017-BreabanSG: Efficient synchronization methods for LET-based applications on a Multi-Processor System on Chip (GB, SS, KG), pp. 1721–1726.
DATE-2017-WangWHTCY: Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks (XW, HW, JH, SXDT, YC, SY), pp. 1727–1732.
DATE-2017-SultanS: A fast leakage aware thermal simulator for 3D chips (HS, SRS), pp. 1733–1738.
DATE-2017-RedaB: Blind identification of power sources in processors (SR, AB), pp. 1739–1744.
DATE-2017-LuJ: Fast low power rule checking for multiple power domain design (CPL, IHRJ), pp. 1745–1750.
DATE-2017-SokolovDKLMY: Benefits of asynchronous control for analog electronics: Multiphase buck case study (DS, VD, VK, DL, AM, AY), pp. 1751–1756.
DATE-2017-ChenCGL: High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC (NCC, PYC, HEG, MPHL), pp. 1757–1762.
DATE-2017-MaityDS: Adaptive interference rejection in Human Body Communication using variable duty cycle integrating DDR receiver (SM, DD, SS), pp. 1763–1768.
DATE-2017-ZengLWS: Efficient storage management for aged file systems on persistent memory (KZ, YL, HW0, JS), pp. 1769–1774.
DATE-2017-RazlighiIKR: LookNN: Neural network with no multiplication (MSR, MI, FK, TR), pp. 1775–1780.
DATE-2017-MohrT: Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores (MM, CT), pp. 1781–1786.
DATE-2017-IbrahimC: Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology (MI0, KC), pp. 1787–1792.
DATE-2017-McDanielGB: The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips (JM, WHG, PB), pp. 1793–1798.
DATE-2017-PotluriSHPM: Synthesis of on-chip control circuits for mVLSI biochips (SP, AS, MHP, PP, JM), pp. 1799–1804.
DATE-2017-ChenS0H: Scheduling and optimization of genetic logic circuits on flow-based microfluidic biochips (YJC, SS0, SR0, TYH), pp. 1805–1810.

David Atienza, Giorgio Di NataleProceedings of the 21st Conference and Exhibition on Design, Automation and Test in EuropeDATE, 2017.

Contents (337 items)

David Atienza, Giorgio Di Natale
Proceedings of the 21st Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2017.