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Travelled to:
1 × China
3 × USA
Collaborated with:
J.Torrellas S.Feng S.Gupta S.A.Mahlke A.Agrawal A.K.Mishra J.Xu P.Jain
Talks about:
chip (3) refresh (2) variat (2) energi (2) minim (2) core (2) cach (2) multiprocessor (1) probabilist (1) lightweight (1)

Person: Amin Ansari

DBLP DBLP: Ansari:Amin

Contributed to:

HPCA 20142014
HPCA 20132013
HPCA 20112011
ASPLOS 20102010

Wrote 6 papers:

HPCA-2014-AgrawalAT #energy #locality #named #process
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules (AA, AA, JT), pp. 84–95.
HPCA-2014-AnsariMXT #energy #named #network
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks (AA, AKM, JX, JT), pp. 440–451.
HPCA-2013-AgrawalJAT #multi #named
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (AA, PJ, AA, JT), pp. 400–411.
HPCA-2013-AnsariFGTM #lightweight #named
Illusionist: Transforming lightweight cores into aggressive cores on demand (AA, SF, SG, JT, SAM), pp. 436–447.
HPCA-2011-AnsariFGM #design #named #polymorphism #robust
Archipelago: A polymorphic cache design for enabling robust near-threshold operation (AA, SF, SG, SAM), pp. 539–550.
ASPLOS-2010-FengGAM #fault #named #probability #reliability #string
Shoestring: probabilistic soft error reliability on the cheap (SF, SG, AA, SAM), pp. 385–396.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.