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Travelled to:
1 × Canada
1 × China
2 × USA
Collaborated with:
S.Devadas G.E.Suh P.Kudva G.Gopalakrishnan A.Agrawal A.Ansari J.Torrellas D.Chiou L.Rudolph
Talks about:
intellig (2) embed (2) cach (2) multiprocessor (1) hierarchi (1) techniqu (1) synchron (1) softwar (1) refrint (1) refresh (1)

Person: Prabhat Jain

DBLP DBLP: Jain:Prabhat

Contributed to:

HPCA 20132013
DAC 20032003
DAC 20002000
CAV 19921992

Wrote 4 papers:

HPCA-2013-AgrawalJAT #multi #named
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (AA, PJ, AA, JT), pp. 400–411.
DAC-2003-JainSD #embedded
Embedded intelligent SRAM (PJ, GES, SD), pp. 869–874.
DAC-2000-ChiouJRD #embedded #memory management #using
Application-specific memory management for embedded systems using software-controlled caches (DC, PJ, LR, SD), pp. 416–419.
CAV-1992-JainKG #scalability #towards #verification
Towards a Verification Technique for Large Synchronous Circuits (PJ, PK, GG), pp. 109–122.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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