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Travelled to:
1 × China
8 × USA
Collaborated with:
C.R.Das V.Narayanan O.Mutlu R.Iyer R.Das J.Xu J.Torrellas A.Jog A.Ansari V.Saripalli S.Datta S.Eachempati N.Vijaykrishnan C.Xu Y.Xie O.Kayiran N.C.Nachiappan M.T.Kandemir C.Nicopoulos D.Park R.R.Iyer M.S.Yousif X.Jiang L.Zhao Z.Fang S.Srinivasan S.Makineni P.Brett N.P.Carter A.Agrawal S.Borkar R.Cledat H.David D.Dunning J.B.Fryman I.Ganev R.A.Golliver R.C.Knauerhase R.Lethin B.Meister W.R.Pinfold J.Teller N.Vasilache G.Venkatesh
Talks about:
perform (4) chip (4) network (3) cmps (3) cach (3) architectur (2) heterogen (2) schedul (2) energi (2) effici (2)

Person: Asit K. Mishra

DBLP DBLP: Mishra:Asit_K=

Contributed to:

HPCA 20142014
ASPLOS 20132013
DAC 20132013
HPCA 20132013
DAC 20122012
DAC 20112011
HPCA 20112011
HPCA 20092009
HPCA 20082008

Wrote 9 papers:

HPCA-2014-AnsariMXT #energy #named #network
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks (AA, AKM, JX, JT), pp. 440–451.
ASPLOS-2013-JogKNMKMID #array #concurrent #named #owl #performance #scheduling #thread
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (AJ, OK, NCN, AKM, MTK, OM, RI, CRD), pp. 395–406.
DAC-2013-MishraMD #approach #design #multi
A heterogeneous multiple network-on-chip design: an application-aware approach (AKM, OM, CRD), p. 10.
HPCA-2013-CarterABCDDFGGKLMMPTTVVX #architecture #named #ubiquitous
Runnemede: An architecture for Ubiquitous High-Performance Computing (NPC, AA, SB, RC, HD, DD, JBF, IG, RAG, RCK, RL, BM, AKM, WRP, JT, JT, NV, GV, JX), pp. 198–209.
DAC-2012-JogMXXNID #architecture #performance
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
DAC-2011-SaripalliMDN #energy #hybrid
An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (VS, AKM, SD, VN), pp. 729–734.
HPCA-2011-JiangMZIFSMBD #named #scheduling #symmetry
ACCESS: Smart scheduling for asymmetric cache CMPs (XJ, AKM, LZ, RI, ZF, SS, SM, PB, CRD), pp. 527–538.
HPCA-2009-DasEMVD #design #evaluation
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs (RD, SE, AKM, NV, CRD), pp. 175–186.
HPCA-2008-DasMNPNIYD #architecture #optimisation #performance
Performance and power optimization through data compression in Network-on-Chip architectures (RD, AKM, CN, DP, VN, RRI, MSY, CRD), pp. 215–225.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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